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參數(shù)資料
| 型號： | SiI161ACT100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SiI 161A PanelLink Receiver |
| 中文描述： | 精工161A條PanelLink接收機 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大?。?/td> | 260K |
| 代理商： | SII161ACT100 |
S ilic on Image, Inc .
SiI 161
A
SiI
-DS-0009-D
S ilic on Image, Inc .
10
Subject to Change without Notice
Configuration Pins Description
Pin Name
Pin # Type Description
OCK_INV
100
In
ODCK Polarity. A LOW level selects normal ODCK output. A HIGH level selects
inverted ODCK output. All other output signals are not affected by this pin. They will
maintain the same timing no matter the setting of OCK_INV pin (See Fig. 8 on p.10).
NOTE OCK_INV cannot be set HIGH (inverted) when operating in Dual Link Mode
Pixel Select. A LOW level indicates one pixel (up to 24-bits) per clock mode using
QE[23:0]. A HIGH level indicates two pixels (up to 48-bits) per clock mode using
QE[23:0] for first pixel and QO[23:0] for second pixel.
Master/Slave. When S_D pin is HIGH (Dual Link), this pin becomes M_S. When
HIGH, it is in Master mode. When LOW, it is in Slave mode. The Master receiver is in
one/two-pixels per clock mode depending upon Dual/Single (S_D) Link operation. The
Slave receiver is always in one-pixel per clock mode.
Staggered Output. A HIGH level selects normal simultaneous outputs on all odd and
even data lines. A LOW level selects staggered output drive. This function is only
available in 2-pixels per clock mode.
Synchronization. When S_D pin is HIGH (Dual Link), this pin is used to synchronize
the Slave receiver to the Master receiver. The SYNC input pin of the Slave receiver is
connected to the DE output pin of the Master receiver.
Output Drive. A HIGH level selects HIGH output drive strength. A LOW level selects
LOW output drive strength.
Single/Dual Link Mode. When HIGH, it is in Dual Link Mode. When LOW it is in Single
Link Mode. The Slave receiver is always in Dual Link mode. The Master receiver
switches between Single and Dual Link mode depending upon the SCDT output of the
Slave receiver that is connected to the S_D input of the Master receiver.
PIXS/M_S
4
In
STAG_OUT/
SYNC
7
In
ST
3
In
S_D
1
In
Power Management Pins Description
Pin
Name
SCDT
8
Out
Pin # Type Description
Sync Detect. A HIGH level is outputted when DE is actively toggling indicating that the
link is alive. A LOW level is outputted when DE is inactive, indicating the link is down.
Can be connected to PDO to power down the outputs when DE is not detected. The
SCDT output itself, however, remains in the active mode at all times.
In Dual Link applications the SCDT pin of the Slave receiver is connected to the S_D pin
of the Master receiver.
Output Driver Power Down (active LOW). A HIGH level indicates normal operation. A
LOW level puts all the output drivers only (except SCDT and CTL1) into a high impedance
(tri-state) mode. A weak internal pull-down device brings each output to ground. PDO is a
sub-set of the PD description. The chip is not in power-down mode with this pin. SCDT
and CTL1 are not tri-stated by this pin.
Power Down (active LOW). A HIGH level indicates normal operation. A LOW level
indicates power down mode. During power down mode, all the output drivers are put into
a high impedance (tri-state) mode. A weak internal pull-down device brings each output to
ground. Additionally, all analog logic is powered down, and all inputs are disabled.
PDO
9
In
PD
2
In
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