參數(shù)資料
型號(hào): SI5364-G-BC
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 26/38頁(yè)
文件大小: 0K
描述: IC PREC PORT CARD CLOCK 99CBGA
標(biāo)準(zhǔn)包裝: 176
系列: DSPLL®
類(lèi)型: 時(shí)鐘發(fā)生器
PLL:
輸入: 時(shí)鐘
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 3:4
差分 - 輸入:輸出: 是/是
頻率 - 最大: 675MHz
除法器/乘法器: 無(wú)/是
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -20°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 99-BCBGA
供應(yīng)商設(shè)備封裝: 99-CBGA(11x11)
包裝: 托盤(pán)
其它名稱(chēng): 336-1280
Si5364
32
Rev. 2.5
C3
INCDELAY
I*
LVTTL
Increment Output Phase Delay.
The INCDELAY and DECDELAY pins can adjust the
phase of the Si5364 clock outputs. Adjustment is
accomplished by driving a pulse (a transition from
low to high and then back to low) into one of the pins
while the other pin is held at a logic low level.
Each pulse on the INCDELAY pin adds a fixed delay
to the Si5364’s clock outputs. The fixed delay time is
equal to twice the period of the 622 MHz output clock
(tDELAY =2/fo_622). The frequency of the 622 MHz
output clock (fo_622) is nominally 32x the frequency of
the input clock. The frequency of the 622 MHz output
clock (fo_622) is scaled additionally according to the
setting of the FEC[1:0] pins.
When the phase of the Si5364 clock outputs is
adjusted using the INCDELAY and/or DECDELAY
pins, the output clock moves to its new phase setting
at a rate of change that is determined by the setting
of the BWSEL[1:0] pins.
Note:
INCDELAY is ignored when the Si5364 is operating
in digital hold (DH) mode.
C4
DECDELAY
I*
LVTTL
Decrement Output Phase Delay.
The INCDELAY and DECDELAY pins can adjust the
phase of the Si5364 clock outputs. Adjustment is
accomplished by driving a pulse (a transition from
low to high and then back to low) into one of the pins
while the other pin is held at a logic low level.
Each pulse on the DECDELAY pin removes a fixed
delay from the Si5364’s clock outputs. The fixed
delay time is equal to twice the period of the 622
MHz output clock (tDELAY =2/fo_622). The frequency
of the 622 MHz output clock (fo_622) is nominally 32x
the frequency of the input clock. The frequency of the
622 MHz output clock (fo_622) is scaled additionally
according to the setting of the FEC[1:0] pins.
When the phase of the Si5364 clock outputs is
adjusted using the INCDELAY and/or DECDELAY
pins, the output clock moves to its new phase setting
at a rate of change that is determined by the setting
of the BWSEL[1:0] pins.
Note:
INCDELAY is ignored when the Si5364 is operating
in digital hold (DH) mode.
Table 10. Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
*Note:
The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
low state if the input is not driven from an external source.
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