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參數(shù)資料
| 型號(hào)： | SI5364-G-BC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 13/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PREC PORT CARD CLOCK 99CBGA |
| 標(biāo)準(zhǔn)包裝： | 176 |
| 系列： | DSPLL® |
| 類型： | 時(shí)鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 675MHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -20°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 99-BCBGA |
| 供應(yīng)商設(shè)備封裝： | 99-CBGA（11x11） |
| 包裝： | 托盤 |
| 其它名稱： | 336-1280 |
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Si5364
20
Rev. 2.5
2.6. 8 kHz Frame Sync
The Si5364 FSYNC output provides a sync pulse output
stream at an 8 kHz nominal rate. The frequency is
derived by dividing down the VCO clock output
frequency. The FSYNC output pulse stream is time
aligned by providing a rising edge on the SYNCIN input
pin. See Figure 3 on page 6. The FSYNC output is
disabled when 255/238 FEC scaling of the clock output
frequencies is selected or when the DSBLFSYNC input
is active.
2.7. Reset
The Si5364 provides a Reset/Calibration pin, RSTN/
CAL, which resets the device and disables the outputs.
When the RSTN/CAL pin is driven low, the internal
circuitry enters into the reset mode, and all LVTTL
outputs are forced into a high impedance state. Also,
the CLKOUT_n+ and CLKOUT_n– pins are forced to a
nominal CML logic LOW and HIGH respectively (See
Figure 12). The FRQSEL_n[1:0] setting must be set to
01, 10, or 11 to enable this mode. This feature is useful
for in-circuit test applications. A low-to-high transition on
RSTN/CAL initializes all digital logic to a known
condition and initiates self-calibration of the DSPLL. At
the completion of self-calibration, the DSPLL begins to
lock to the clock input signal.
Figure 12. CLKOUT_n± Equivalent Circuit,
RSTN/CAL asserted LOW
2.8. PLL Self-Calibration
The Si5364 achieves optimal jitter performance by
using self-calibration circuitry to set the VCO center
frequency and loop gain parameters within the DSPLL.
Internal circuitry generates self calibration automatically
on powerup or after a loss-of-power condition. Self-
calibration can also be manually initiated by a low-to-
high transition on the RSTN/CAL input.
Self-calibration should be manually initiated after
changing the state of the FEC[1:0] inputs. Whether
manually initiated or automatically initiated at powerup,
the self-calibration process requires the presence of a
valid input clock.
If the self-calibration is initiated without a valid clock
present, the device waits for a valid clock before
completing the self-calibration. The Si5364 clock output
is set to the lower end of the operating frequency range
while the device waits for a valid clock. After the clock
input is validated, the calibration process runs to
completion, the device locks to the clock input, and the
clock output shifts to its target frequency. Subsequent
losses of the input clock signal do not require re-
calibration. If the clock input is lost following self-
calibration, the device enters digital hold mode. When
the input clock returns, the device re-locks to the input
clock without performing a self-calibration. During the
calibration process, the output clock frequency is
indeterminate and may jump as high as 5% above the
final locked value.
2.9. Bias Generation Circuitry
The Si5364 uses an external resistor to set internal bias
currents. The external resistor generates precise bias
currents that significantly reduce power consumption
and variation compared with traditional implementations
that use an internal resistor. The bias generation
circuitry requires a 10 k
Ω (1%) resistor connected
between REXT and GND.
2.10. Differential Input Circuitry
The Si5364 provides differential inputs for the CLKIN_A,
CLKIN_B, and REF/CLKIN_F clock inputs. These inputs
on page 7) and are driven by differential or single-ended
driver circuits. The termination resistor is connected
externally as shown.
2.11. Differential Output Circuitry
The Si5364 uses current mode logic (CML) output
drivers to provide the clock outputs CLKOUT[3:0]. For
single-ended operation, leave one CLKOUT line
unconnected.
2.12. Power Supply Connections
The Si5364 incorporates an on-chip voltage regulator.
The
voltage
regulator
requires
an
external
compensation circuit of one resistor and one capacitor
to ensure stability in all operating conditions.
Internally, the Si5364 VDD33 pins are connected to the
on-chip voltage regulator input, and the VDD33 pins also
supply power to the device’s LVTTL I/O circuitry. The
VDD25 pins supply power to the core DSPLL circuitry
100
Ω
VDD 2.5 V
100
Ω
CLKOUT_n–
CLKOUT_n+
15 mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI5364-H-BL | IC CLK MULT SONET/SDH 99-PBGA |
| SI5365-C-GQ | IC CLOCK MULTIPLIER PROG 100TQFP |
| SI5366-C-GQ | IC CLOCK MULTIPLIER PREC 100TQFP |
| SI5367A-C-GQ | IC CLOCK MULTIPLIER PROG 100TQFP |
| SI5368A-C-GQ | IC CLK MULTIPLIER ATTEN 100TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Si5364-H-BL | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Prcsn Port Card Clock Multiplr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5364-H-BLR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precision 19MHz 155MHz 622MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5364-H-GL | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Prcsn Port Card Clock Multiplr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5364-H-GLR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precision 19MHz 155MHz 622MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5365 | 制造商:SILABS 制造商全稱:SILABS 功能描述:PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER |
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