參數(shù)資料
型號： SI5338-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 27/44頁
文件大小： 0K
描述： BOARD EVALUATION SI5338
標準包裝： 1
主要目的： 計時，時鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： Si5338
主要屬性： LVPECL/LVDS：160 kHz 至 700 MHz，<1 ps RMS 標準抖動，零 ppm 頻率錯誤
次要屬性： 基于 USB 的 GUI，用于編程，I2C/SMBus 兼容接口，1.8、2.5 或 3.3 V
已供物品： 板，線纜，CD，樣品
產(chǎn)品目錄頁面： 628 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： 336-1555-5-ND - IC CLK GEN QUAD 200MHZ 24-QFN
336-1554-5-ND - IC CLK GEN QUAD 350MHZ 24-QFN
336-1553-5-ND - IC CLK GEN QUAD 700MHZ 24-QFN
其它名稱： 336-1556
Si5338
Rev. 1.3
33
3IN3
I
Multi
This pin can have one of the following functions depending on the
part number:
CLKIN (for Si5338A/B/C and Si5338N/P/Q devices only)
Provides a high-impedance clock input for single ended clock
signals. This input should be dc-coupled as shown in “3.2. Input
If this pin is not used, it should be connected to ground.
PINC (for Si5338D/E/F devices only)
Used as the phase increment pin. See "3.10.2. Output Phase
Increment/Decrement" on page 26 for more details. Minimum
pulse width of 100 ns is required for proper operation. If this pin is
not used, it should be connected to ground.
FINC (for Si5338G/H/J devices only)
Used as the frequency increment pin. See "3.10.1. Frequency
Increment/Decrement" on page 26 for more details. Minimum
pulse width of 100 ns is required for proper operation. If this pin is
not used, it should be connected to ground.
OEB (for Si5338K/L/M devices only)
Used as an output enable pin. 0 = All outputs enabled; 1 = All
outputs disabled. By default, outputs are tri-stated when disabled.
4IN4
I
Multi
This pin can have one of the following functions depending on the
part number
I2C_LSB (for Si5338A/B/C and Si5338K/L/M devices only)
This is the LSB of the Si5338 I2C address. 0 = I2C address
70h (111 0000), 1 = I2C address 71h (111 0001).
FDBK (for Si5338N/P/Q devices only)
Provides a high-impedance feedback input for single-ended clock
signals. This input should be dc-coupled as shown in “3.2. Input
Stage”, Figure 3. If this pin is not used, it should be connected to
ground.
PDEC (for Si5338D/E/F) devices only)
Used as the phase decrement pin. See “3.10.2. Output Phase
Increment/Decrement” for more details. Minimum pulse width of
100 ns is required for proper operation. If this pin is not used, it
should be connected to ground.
FDEC (for Si5338G/H/J devices only)
Used as the frequency decrement pin. See “3.10.1. Frequency
Increment/Decrement” for more details. Minimum pulse width of
100 ns is required for proper operation. If this pin is not used, it
should be connected to ground.
Table 16. Si5338 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Type
Description
相關(guān)PDF資料
PDF描述
H3AAH-2606G IDC CABLE - HSC26H/AE26G/HSC26H
0982660138 CBL 12POS 0.5MM JMPR TYPE D 1'
0982661084 CBL 37POS 0.5MM JMPR TYPE D 6"
HMC08DRTH CONN EDGECARD 16POS DIP .100 SLD
EBC43DCSD-S288 CONN EDGECARD 86POS .100 EXTEND
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI5338F-A01839-GM 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk
SI5338F-A01839-GMR 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel
Si5338F-A-GM 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C-PRGRMBL clock generatr 0.16-200MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SI5338F-A-GMR 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C-Program Clk Gen 0.16-200MHz Pin-Ctrl RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
Si5338F-B-GM 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C-PRGRMBL clock generatr 0.16-200MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*