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參數(shù)資料
| 型號： | SI5318 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| 中文描述： | SONET / SDH的精密時鐘倍頻集成電路 |
| 文件頁數(shù)： | 24/30頁 |
| 文件大?。?/td> | 593K |
| 代理商： | SI5318 |
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Si5318
24
Rev. 1.0
H6
H7
CLKOUT+
CLKOUT–
O
CML
Differential Clock Output.
High frequency clock output. The frequency of the
CLKOUT output is a multiple of the frequency of the
CLKIN input. The input-to-output frequency multipli-
cation factor is set by selecting the clock input range
and the clock output range. The frequency of the
CLKOUT clock output can be in the 19 or 155 MHz
range as indicated in Table 3 on page 7. The clock
output frequency is selected using the FRQSEL[1:0]
pins. The clock input frequency is selected using the
INFRQSEL[2:0] pins.
H5
H8
FRQSEL[0]
FRQSEL[1]
I*
LVTTL
Clock Output Frequency Range Select
Select frequency range of the clock output, CLKOUT.
(See Table 3 on page 7.)
00 = Clock Driver Powerdown.
01 = 19 MHz Frequency Range.
10 = 155 MHz Frequency Range.
11 = Reserved.
B1
C1
BWSEL[0]
BWSEL[1]
I*
LVTTL
Bandwidth Select.
BWSEL[1:0] pins set the bandwidth of the loop filter
within the DSPLL to 6400, 3200, 1600, or 800 Hz as
indicated below.
00 = 3200 Hz
01 = 1600 Hz
10 = 800 Hz
11 = 6400 Hz
Note:
The loop filter bandwidth will be twice the value
indicated when DBLBW is set high.
E8
CAL_ACTV
O
LVTTL
Calibration Mode Active.
This output is driven high during the DSPLL self-cali-
bration and the subsequent initial lock acquisition
period.
H4
VALTIME
I*
LVTTL
Clock Validation Time for LOS.
VALTIME sets the clock validation times for recovery
from an LOS alarm condition. When VALTIME is
high, the validation time is approximately
13 seconds. When VALTIME is low, the validation
time is approximately 100 ms.
A2, A3, B2,
B3, B6, B7,
C8
RSVD_GND
—
LVTTL
Reserved—GND.
This pin must be tied to GND for normal operation.
Table 10. Si5318 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
*Note:
The LVTLL inputs on the Si5318 device have an internal pulldown mechanism that causes these inputs to default to a
logic low state if the input is not driven from an external source.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5318-EVB | 功能描述:時鐘和定時器開發(fā)工具 SI5318 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5318-F-BC | 功能描述:時鐘合成器/抖動清除器 SONET/SDH PRECISION CLOCK MULT.IC 19/155 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5318-F-BCR | 功能描述:IC MULTIPLIER SONET/SDH 63CBGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:DSPLL® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SI5318-G-BC | 功能描述:電信集成電路 SONET/SDH Precision Clock Multiplier IC RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| SI5319 | 制造商:SILABS 制造商全稱:SILABS 功能描述:ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR |
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