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參數(shù)資料
| 型號： | SI5318 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| 中文描述： | SONET / SDH的精密時鐘倍頻集成電路 |
| 文件頁數(shù)： | 16/30頁 |
| 文件大小： | 593K |
| 代理商： | SI5318 |
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Si5318
16
Rev. 1.0
2.3.3. Jitter Tolerance
Jitter tolerance for the Si5318 is defined as the
maximum peak-to-peak sinusoidal jitter that can be
present on the incoming clock. The tolerance is a
function of the jitter frequency, because tolerance
improves for lower input jitter frequency. See Figure 7.
Figure 7. Jitter Tolerance Mask/Template
2.4. Digital Hold of the PLL
When no valid input clock is available, the Si5318
digitally holds the internal oscillator to its last frequency
value. This provides a stable clock to the system until an
input clock is again valid. This clock maintains very
stable operation in the presence of constant voltage and
temperature. The frequency accuracy specifications for
digital hold mode are given in Table 4 on page 8.
2.5. Hitless Recovery from Digital Hold
When the Si5318 device is locked to a valid input clock,
a loss of the input clock causes the device to
automatically switch to digital hold mode. When the
input clock signal returns, the device performs a
“hitless” transition from digital hold mode back to the
selected input clock. That is, the device performs
“phase build-out” to absorb the phase difference
between the internal VCO clock operating in digital hold
mode and the new/returned input clock. The maximum
phase step size seen at the clock output during this
transition and the maximum slope for this phase step
are given in Table 4 on page 8.
This feature can be disabled by asserting the
FXDDELAY pin. When the FXDDELAY pin is high, the
output clock is phase and frequency locked with a
known phase relationship to the input clock.
Consequently, any abrupt phase change on the input
clock propagates through the device, and the output
slews at the selected loop bandwidth until the original
phase relationship is restored.
Note:
When the DBLBW is asserted, hitless recovery must
also be disabled by driving FXDDELAY high for proper
operation.
Figure 8. Recovery from Digital Hold
2.6. Loss-of-Signal Alarm
The Si5318 has loss-of-signal (LOS) circuitry that
constantly monitors the CLKIN input clock for missing
pulses. The LOS circuitry sets a LOS output alarm
signal when missing pulses are detected.
The LOS circuitry operates as follows. Regardless of
the selected input clock frequency range, the LOS
circuitry divides down the input clock into the 19 MHz
range. The LOS circuitry then over-samples this
divided-down input clock to search for extended periods
of time without input clock transitions. If the LOS
circuitry detects four consecutive samples of the
divided-down input clock that are the same state (i.e.,
1111 or 0000), a LOS condition is declared, the Si5318
goes into digital hold mode, and the LOS output alarm
signal is set high. The LOS sampling circuitry runs at a
frequency of f
O_155/2
, where f
O_155
is the output clock
frequency when the FRQSEL[1:0] pins are set to 10.
Table 3 on page 7 lists the minimum and maximum
transitionless time periods required for declaring a LOS
on the input clock (t
LOS
).
Once the LOS alarm is asserted, it is held high until the
input clock is validated over a time period designated by
the VALTIME pin. When VALTIME is low, the validation
time period is about 100 ms. When VALTIME is high,
the validation time period is about 13 s. If another LOS
condition is detected on the input clock during the
validation time (i.e., if another set of 1111 or 0000
samples are detected), the LOS alarm remains
asserted, and the validation time starts over. When the
LOS alarm is finally released, the Si5318 exits digital
hold mode and locks to the input clock. The LOS alarm
is automatically set high at power-on and at every low-
to-high transition of the RSTN/CAL pin. In these cases,
the Si5318 undergoes a self-calibration before releasing
the LOS alarm and locking to the input clock.
Input
Jitter
Amplitude
10 ns
F
BW
–20 dB/dec.
f
Jitter In
Excessive Input Jitter Range
Recovery from
Digital Hold
m
PT
t
PT_MTIE
C
t
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SI5318-EVB | 功能描述:時鐘和定時器開發(fā)工具 SI5318 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5318-F-BC | 功能描述:時鐘合成器/抖動清除器 SONET/SDH PRECISION CLOCK MULT.IC 19/155 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5318-F-BCR | 功能描述:IC MULTIPLIER SONET/SDH 63CBGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:DSPLL® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SI5318-G-BC | 功能描述:電信集成電路 SONET/SDH Precision Clock Multiplier IC RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| SI5319 | 制造商:SILABS 制造商全稱:SILABS 功能描述:ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR |
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