- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374788 > SI5318 (Electronic Theatre Controls, Inc.) SONET/SDH PRECISION CLOCK MULTIPLIER IC PDF資料下載
參數(shù)資料
| 型號(hào)： | SI5318 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| 中文描述： | SONET / SDH的精密時(shí)鐘倍頻集成電路 |
| 文件頁數(shù)： | 23/30頁 |
| 文件大?。?/td> | 593K |
| 代理商： | SI5318 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
Si5318
Rev. 1.0
23
F1
G1
H1
INFRQSEL[0]
INFRQSEL[1]
INFRQSEL[2]
I*
LVTTL
Input Frequency Range Select.
Pins(INFRQSEL[2:0]) select the frequency range for
the input clock, CLKIN. (See Table 3 on page 7.)
000 = Reserved.
001 = 19 MHz range.
010 = 39 MHz range.
011 = 78 MHz range.
100 = 155 MHz range.
101 = Reserved.
110 = Reserved.
111 = Reserved.
F8
LOS
O
LVTTL
Loss-of-Signal (LOS) Alarm for CLKIN.
Active high output indicates that the Si5318 has
detected missing pulses on the input clock signal.
The LOS alarm is cleared after either 100 ms or
13 seconds of a valid CLKIN clock input, depending
on the setting of the VALTIME input.
D8
DH_ACTV
O
LVTTL
Digital Hold Mode Active.
Active high output indicates that the DSPLL is in
digital hold mode. Digital hold mode locks the current
state of the DSPLL and forces the DSPLL to continue
generation of the output clock with no additional
phase or frequency information from the input clock.
H3
RSTN/CAL
I*
LVTTL
Reset/Calibrate.
When low, the internal circuitry enters the reset mode
and all LVTTL outputs are forced into a high-imped-
ance state. Also, the CLKOUT+ and CLKOUT– pins
are forced to a nominal CML logic LOW and HIGH
respectively. This feature is useful for in-circuit test
applications.
A low-to-high transition on RSTN/CAL initializes all
digital logic to a known condition, enables the device
outputs, and initiates self-calibration of the DSPLL.
Upon completion of self-calibration, the DSPLL
begins to lock to the selected clock input signal.
Table 10. Si5318 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
*Note:
The LVTLL inputs on the Si5318 device have an internal pulldown mechanism that causes these inputs to default to a
logic low state if the input is not driven from an external source.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI5320 | SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| SI5320-EVB | EVALUATION BOARD FOR Si5320 SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| SI5320-X-BC | SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| Si5321 | SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| SI5364 | SONET/SDH PRECISION PORT CARD CLOCK IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5318-EVB | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 SI5318 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5318-F-BC | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 SONET/SDH PRECISION CLOCK MULT.IC 19/155 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5318-F-BCR | 功能描述:IC MULTIPLIER SONET/SDH 63CBGA RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:DSPLL® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SI5318-G-BC | 功能描述:電信集成電路 SONET/SDH Precision Clock Multiplier IC RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| SI5319 | 制造商:SILABS 制造商全稱:SILABS 功能描述:ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。