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Section 7
7.1
Bus State Controller (BSC)
.......................................................................... 249
Overview............................................................................................................................ 249
7.1.1
Features................................................................................................................. 249
7.1.2
Block Diagram...................................................................................................... 251
7.1.3
Pin Configuration.................................................................................................. 252
7.1.4
Register Configuration.......................................................................................... 254
7.1.5
Address Map......................................................................................................... 255
Register Descriptions......................................................................................................... 257
7.2.1
Bus Control Register 1 (BCR1)............................................................................ 257
7.2.2
Bus Control Register 2 (BCR2)............................................................................ 260
7.2.3
Bus Control Register 3 (BCR3)............................................................................ 261
7.2.4
Wait Control Register 1 (WCR1) ......................................................................... 263
7.2.5
Wait Control Register 2 (WCR2) ......................................................................... 265
7.2.6
Wait Control Register 3 (WCR3) ......................................................................... 267
7.2.7
Individual Memory Control Register (MCR)....................................................... 268
7.2.8
Refresh Timer Control/Status Register (RTCSR) ................................................ 272
7.2.9
Refresh Timer Counter (RTCNT) ........................................................................ 274
7.2.10 Refresh Time Constant Register (RTCOR).......................................................... 274
Access Size and Data Alignment....................................................................................... 275
7.3.1
Connection to Ordinary Devices .......................................................................... 275
7.3.2
Connection to Little-Endian Devices.................................................................... 277
Accessing Ordinary Space................................................................................................. 278
7.4.1
Basic Timing......................................................................................................... 278
7.4.2
Wait State Control ................................................................................................ 283
7.4.3
CS
Assertion Period Extension ............................................................................ 287
Synchronous DRAM Interface .......................................................................................... 288
7.5.1
Synchronous DRAM Direct Connection.............................................................. 288
7.5.2
Address Multiplexing............................................................................................ 290
7.5.3
Burst Reads........................................................................................................... 292
7.5.4
Single Reads.......................................................................................................... 297
7.5.5
Single Writes ........................................................................................................ 299
7.5.6
Burst Write Mode ................................................................................................. 300
7.5.7
Bank Active Function........................................................................................... 303
7.5.8
Refreshes............................................................................................................... 313
7.5.9
Overlap Between Auto Precharge Cycle (Tap) and Next Access ........................ 316
7.5.10 Power-On Sequence.............................................................................................. 317
7.5.11 64 Mbit Synchronous DRAM (2 Mword
×
32 Bit) Connection........................... 319
DRAM Interface................................................................................................................ 320
7.6.1
DRAM Direct Connection.................................................................................... 320
7.6.2
Address Multiplexing............................................................................................ 321
7.6.3
Basic Timing......................................................................................................... 322
7.6.4
Wait State Control ................................................................................................ 323
7.6.5
Burst Access.......................................................................................................... 325
7.2
7.3
7.4
7.5
7.6