
261
Bits 5 and 4—Bus Size Specification for Area 2 (CS2) (A2SZ1, A2SZ0): Effective only when
ordinary space is set.
Bit 5: A2SZ1
Bit 4: A2SZ0
Description
0
0
Reserved (do not set)
1
Byte (8-bit) size
1
0
Word (16-bit) size
1
Longword (32-bit) size
(Initial value)
Bits 3 and 2—Bus Size Specification for Area 1 (CS1) (A1SZ1, A1SZ0)
Bit 3: A1SZ1
Bit 2: A1SZ0
Description
0
0
Reserved (do not set)
1
Byte (8-bit) size
1
0
Word (16-bit) size
1
Longword (32-bit) size
(Initial value)
Bits 1 and 0—Reserved: These bits are always read as 0. The write value should always be 0.
7.2.3
Bus Control Register 3 (BCR3)
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
A4LW2
AHLW2
A1LW2
A0LW2
Initial value:
0
R
0
R
0
R
0
R
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
DSWW1 DSWW0
—
—
—
BASEL
EDO
BWE
Initial value:
0
0
0
R
0
R
0
R
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
Initialize the BASEL, EDO, and BWE bits after a power-on reset and do not write to them
thereafter. To change other bits by writing to them, write the same value as they are initialized to.
Do not access any space other than CS0 until the register initialization ends.
Bits 15 to 12—Reserved bits: These bits are always read as 0. The write value should always be 0.
Bits 11 to 8—Long Wait Specification for Areas 0 to 4 (AnLW2): When the basic memory
interface setting is made for CS n, from 3 to 14 wait cycles are inserted in CS n accesses,