參數(shù)資料
型號(hào)： SC5554MVR132
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 51/58頁(yè)
文件大?。?/td> 0K
描述： MCU MPC5554 DP ONLY 416-PBGA
標(biāo)準(zhǔn)包裝： 200
系列： MPC55xx Qorivva
核心處理器： e200z6
芯體尺寸： 32-位
速度： 132MHz
連通性： CAN，EBI/EMI，SCI，SPI
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 256
程序存儲(chǔ)器容量： 2MB（2M x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.35 V ~ 1.65 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 40x12b
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 416-TBGA
包裝： 托盤
Revision History for the MPC5554 Data Sheet
MPC5554 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
55
Last paragraph: Changed the first sentence FROM , , , the voltage on the pins goes to high-impedance until . . .
TO. . .the pins go to a high-impedance state until . . .
Last sentence: Changed from: ‘This ensures that the digital 1.5 V logic, which is reset by the ORed POR only and
can cause the 1.5 V supply to decrease below its specification, is reset properly.’
To: ‘This ensures that the digital 1.5 V logic, which is reset only by an ORed POR and can cause the 1.5 V supply
to decrease less than its specification, resets correctly.’
Added the following NOTE before the 416 BGA Map:
NOTE
The MPC5500 devices are pin compatible for software portability and use the primary
function names to label the pins in the BGA diagram. Although some devices do not support
all the primary functions shown in the BGA diagram, the muxed and GPIO signals on those
pins remain available. See the signals chapter in the device reference manual for the signal
muxing.
Changed footnote 2 from:
‘Device failure is defined as: ‘If after exposure to ESD pulses, the device no longer meets the device specification
requirements. Complete DC parametric and functional testing will be performed per applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.’
to:
Device failure is defined as: ‘If after exposure to ESD pulses, the device does not meet the device specification
requirements, which includes the complete DC parametric and functional testing at room temperature and hot
temperature.
Table 6 (VRC and POR Electrical Specifications) VCR/POR Electrical Specifications:
Added footnote 1 to specs 1, 2, and 3 that reads: The internal POR signals are VPOR15, VPOR33, and VPOR5.
On power up, assert RESET before the internal POR negates. RESET must remain asserted until the power
supplies are within the operating conditions as specified in Table 9 DC Electrical Specifications. On power down,
assert RESET before any power supplies fall outside the operating conditions and until the internal POR asserts.
Reformatted columns.
Added footnote that reads: VDDE2 and VDDE3 are limited to 2.25–3.6 V only if SIU_ECCR[EBTS] = 0; VDDE2 and
VDDE3 have a range of 1.6–3.6 V if SIU_ECCR[EBTS] =1.
Added (TA = TL to TH) to the table title.
Table 14 (Flash Program and Erase Specifications (TA = TL to TH)) Flash Program and Erase Specifications (TA = TL to TH)
Footnote 1, Changed ‘Typical program and erase times assume nominal supply values and operation at 25 oC’
to ‘Typical program and erase times are calculated at 25 oC operating temperature using nominal supply values..’
Table 17 (Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)) Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)
Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’
Table 19 (Reset and Configuration Pin Timing) Reset and Configuration Pin Timing:
Footnote 1: Removed VDD = 1.35–1.65 V.
Table 28. Changes Between Rev. 2.0 and 3.0 (continued)
Location
Description of Changes
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