參數(shù)資料
型號(hào)： SC403MLTRT
廠商： Semtech
文件頁(yè)數(shù)： 25/32頁(yè)
文件大?。?/td> 741K
描述： IC REG DL BCK/LINEAR SYNC 32MLPQ
標(biāo)準(zhǔn)包裝： 1
系列： EcoSpeed®, SmartDrive™
拓?fù)洌?/td> 降壓（降壓）同步（1），線性（LDO）（1）
功能： 任何功能
輸出數(shù)： 2
頻率 - 開(kāi)關(guān)： 1MHz
電壓/電流 - 輸出 1： 可調(diào)至 0.75V，6A
電壓/電流 - 輸出 2： 可調(diào)至 0.75V，200mA
帶 LED 驅(qū)動(dòng)器： 無(wú)
帶監(jiān)控器： 無(wú)
帶序列發(fā)生器： 是
電源電壓： 3 V ~ 28 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-MLPQ（5x5）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： SC403MLDKR
SC403
25
Applications Information (continued)
Soft Start Capacitor Selection
For a soft-start time (t
SS
) of approximately 3ms, solve the
following equation for C
SS
.
nF
5
.
5
C
V
5
.
1
A
75
.
2
t
C
SS
SS
SS
If C
SS
 is selected as 4.7 nF, then t
SS
 will be 2.6 ms.
Then the PGOOD delay, the time from V
OUT
 regulation to
PGOOD signal high is shown by the following equation.
A
75
.
2
)
V
5
.
1
V
64
.
0
(
nF
7
.
4
t
DD
DELAY
-
PGOOD
At V
DD
 = 5V, the PGOOD delay will be 2.9ms.
Stability Considerations
Unstable operation is possible with adaptive on-time con-
trollers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
250ns minimum off-time has expired. In extreme cases
the noise can cause three or more successive on-times.
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not affect opera-
tion. This form of instability can usually be avoided by
providing the FB pin with a smooth, clean ripple signal
that is at least 10mVp-p, which may dictate the need to
increase the ESR of the output capacitors. It is also impera-
tive to provide a proper PCB layout as discussed in the
Layout Guidelines section.
Another way to eliminate doubling-pulsing is to add a
small (~ 10pF) capacitor across the upper feedback resis-
tor, as shown in Figure 13. This capacitor should be left
unpopulated until it can be confirmed that double-pulsing
exists. Adding the C
TOP
 capacitor will couple more ripple
into FB to help eliminate the problem. An optional con-
nection on the PCB should be available for this capacitor.
V
OUT
To FB pin
R2
R1
C
TOP
Figure 13  Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking sta-
bility is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and
ringing. Ringing for more than one switching cycle after
the initial step is an indication that the ESR should be
increased.
One simple way to solve this problem is to add trace resis-
tance in the high current output path. A side effect of
adding trace resistance is a decrease in load regulation
performance.
ESR Requirements
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide
10mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insuffi-
cient ESR. The on-time control regulates the valley of the
output ripple voltage. This ripple voltage is the sum of the
two voltages. One is the ripple generated by the ESR, the
other is the ripple due to capacitive charging and dis-
charging during the switching cycle. For most applica-
tions the minimum ESR ripple voltage is dominated by the
output capacitors, typically SP or POSCAP devices. For
stability the ESR zero of the output capacitor should be
lower than approximately one-third the switching fre-
quency. The formula for minimum ESR is shown by the
following equation.
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