參數(shù)資料
型號(hào)： SC403MLTRT
廠商： Semtech
文件頁(yè)數(shù)： 19/32頁(yè)
文件大?。?/td> 741K
描述： IC REG DL BCK/LINEAR SYNC 32MLPQ
標(biāo)準(zhǔn)包裝： 1
系列： EcoSpeed®, SmartDrive™
拓?fù)洌?/td> 降壓（降壓）同步（1），線性（LDO）（1）
功能： 任何功能
輸出數(shù)： 2
頻率 - 開(kāi)關(guān)： 1MHz
電壓/電流 - 輸出 1： 可調(diào)至 0.75V，6A
電壓/電流 - 輸出 2： 可調(diào)至 0.75V，200mA
帶 LED 驅(qū)動(dòng)器： 無(wú)
帶監(jiān)控器： 無(wú)
帶序列發(fā)生器： 是
電源電壓： 3 V ~ 28 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-MLPQ（5x5）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： SC403MLDKR
SC403
19
I
PEAK
I
LOAD
I
LIM
Figure 7  Valley Current Limit
Setting the valley current limit to 6A results in a peak induc-
tor current of 6A plus the peak-to-peak ripple current. In
this situation, the average (load) current through the induc-
tor is 6A plus one-half the peak-to-peak ripple current.
The internal 10糀 current source is temperature compen-
sated at 4100ppm in order to provide tracking with the
RDS
ON
.
The R
ILIM
 value is calculated by the following equation.
  R
ILIM
 = 1176 x I
LIM
 x [0.088 x (5V - V
DD
) + 1] (&)
where I
LIM
 is in Amps.
When selecting a value for R
ILIM
 do not exceed the absolute
maximum voltage value for the ILIM pin. Note that because
the low-side MOSFET with low RDS
ON
 is used for current
sensing, the PCB layout, solder connections, and PCB connec-
tion to the LX node must be done carefully to obtain good
results. R
ILIM
 should be connected directly to LXS (pin 28).
Soft-Start of PWM Regulator
SC403 has a programmable soft-start time that is con-
trolled by an external capacitor at the SS pin. After the
controller meets both UVLO and EN/PSV thresholds, the
controller has an internal current source of 2.75礎(chǔ) flowing
through the SS pin to charge the capacitor. During the
start up process (Figure 8), 50% of the voltage at the SS
pin is used as the reference for the FB comparator. The
PWM comparator issues an on-time pulse when the
voltage at the FB pin is less than 50% of the SS pin. As
result, the output voltage follows the SS start voltage. The
output voltage reaches and maintains regulation when
the soft start voltage is > 1.5V. The time between the first
LX pulse and when V
OUT
 meets regulation is the soft start
time (t
SS
). The calculation for the soft-start time is shown
by the following equation.
A
75
.
2
V
5
.
1
C
t
SS
SS
The voltage at the SS pin continues to ramp up and eventu-
ally is equal to 64% of V
DD
. After soft start completes, the FB
pin voltage is compared to an internal reference of 0.75V.
The delay time between the V
OUT
 regulation point and
PGOOD going high is shown by the following equation.
Time (400祍/div)s/div)
/div)
 (10mV/div)
(2V/div)
 
(5V/div)
(500mV/div)
Figure 8  Soft-start Timing Diagram
Pre-Bias Startup
SC403 can start up as if in a soft-start condition with an
existing output voltage level. The soft start time is still the
same as normal start up (when the output voltage starts
from zero). The output voltage starts to ramp up when
one-half of the voltage at SS pin meets the pre-charge FB
voltage level. Pre-bias startup is achieved by turning off
the lower gate when the inductor current falls below zero.
This method prevents the output voltage from
decreasing.
Power Good Output
The PGOOD (power good) output is an open-drain output
which requires a pull-up resistor. When the voltage at the
FB pin is 10% below the nominal voltage, PGOOD is pulled
low. It is held low until the output voltage returns above
92% of nominal.
PGOOD will transition low if the V
FB
 pin exceeds +20% of
nominal, which is also the over-voltage shutdown thresh-
old. PGOOD also pulls low if the EN/PSV pin is low when
V
DD
 voltage is present.
Applications Information (continued)
A
75
.
2
)
V
5
.
1
V
64
.
0
(
C
t
DD
SS
DELAY
-
PGOOD
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