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參數(shù)資料
| 型號： | SC403MLTRT |
| 廠商： | Semtech |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 741K |
| 描述： | IC REG DL BCK/LINEAR SYNC 32MLPQ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | EcoSpeed®, SmartDrive™ |
| 拓?fù)洌?/td> | 降壓（降壓）同步（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 1MHz |
| 電壓/電流 - 輸出 1： | 可調(diào)至 0.75V，6A |
| 電壓/電流 - 輸出 2： | 可調(diào)至 0.75V，200mA |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 是 |
| 電源電壓： | 3 V ~ 28 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-MLPQ（5x5） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | SC403MLDKR |
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SC403
21
Figure 10 shows the ENL voltage thresholds and their
effect on LDO and switcher operation.
AGND
ENL low
threshold
(min 0.4V)
2.6V
2.4V
LDO on
LDO on
LDO off
V
IN
UVLO hysteresis
ENL voltage
Switcher on if EN = high
Switcher on if EN = high
Switcher off by V
IN
UVLO
Figure 10 ENL Threshold
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
ENL pin
V
IN
input voltage
When the ENL pin is high and V
IN
is above the UVLO point,
the LDO will begin start-up. During the initial phase, when
the V
DD
voltage (which is the LDO output voltage) is less
than 0.75V, the LDO initiates a current-limited start-up
(typically 65mA) to charge the output capacitors while
protecting from a short circuit event. When V
DD
is greater
than 0.75V but still less than 90% of its final value (as
sensed at the FBL pin), the LDO current limit is increased
to ~115mA. When V
DD
has reached 90% of the final value
(as sensed at the FBL pin), the LDO current limit is increased
to ~200mA and the LDO output is quickly driven to the
nominal value by the internal LDO regulator. It is recom-
mended that during LDO start-up to hold the PWM
switching off until the LDO has reached 90% of the final
value. This prevents overloading the current-limited LDO
output during the LDO start-up.
Due to the initial current limitations on the LDO during
power up (Figure 11), any external load attached to the
VDD pin must be limited to 20mA before the LDO has
reached 90% of it final regulation value.
1.
2.
V
VLDO
Final
90% of
V
VLDO
Final
Constant current
startup @ ~ 115mA
Voltage regulating
with ~ 200mA
current limit
Short-circuit Protection @ ~ 65mA
0.7V
Figure 11 LDO Start-Up
LDO Switch-Over Operation
The switch-over function is provided to increase efficiency
by using the more efficient DC-DC converter to power the
LDO output, avoiding the less efficient LDO regulator
when possible. The switch-over function connects the
VDD pin directly to the VOUT pin using an internal switch.
When the switch-over is complete the LDO is turned off,
which results in power savings and maximizes efficiency.
If the LDO output is used to bias the SC403, then after
switch-over the device is self-powered from the switching
regulator with the LDO turned off.
The switch-over logic waits for 32 switching cycles before
it starts the switch-over. When the LDO is already in regu-
lation and the DC-DC converter is later enabled, as soon as
the PGOOD output goes high, the 32 cycles are started.
The voltages at the VDD and VOUT pins are then com-
pared; if the two voltages are within ?00mV of each
other, the VDD pin connects to the VOUT pin using an
internal switch, and the LDO is turned off.
Switch-over Limitations on VOUT, ENL, and VDD
Because the internal switch-over circuit always compares
the VOUT and VDD pins at start-up, there are limitations
on permissible combinations of these pins. Consider the
case where V
OUT
is programmed to 3.0V and V
LDO
is pro-
grammed to 3.3V. After start-up, the device would connect
VOUT to VDD and disable the LDO, since the two voltages
are within the ?00mV switch-over window. To avoid
unwanted switch-over, the minimum difference between
the voltages for V
OUT
and V
LDO
should be ?00mV.
Applications Information (continued)
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| SC4040 | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:PRECISION SHUNT VOLTAGE REFERENCE |
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