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參數(shù)資料
| 型號(hào)： | SC16C554B |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs |
| 中文描述： | 5伏，3.3伏和2.5伏兆5四異步/秒（最大），16字節(jié)的FIFO |
| 文件頁數(shù)： | 31/51頁 |
| 文件大?。?/td> | 253K |
| 代理商： | SC16C554B |
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9397 750 13133
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 9 February 2005
31 of 51
Philips Semiconductors
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C554B/554DB and
the CPU.
Table 20:
Bit
7
Line Status Register bits description
Symbol
Description
LSR[7]
FIFO data error.
Logic 0 = No error (normal default condition).
Logic 1 = At least one parity error, framing error or break indication is in the
current FIFO data. This bit is cleared when LSR register is read.
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to
a logic 1 whenever the transmit holding register and the transmit shift register
are both empty. It is reset to logic 0 whenever either the THR or TSR contains
a data character. In the FIFO mode, this bit is set to ‘1’ whenever the transmit
FIFO and transmit shift register are both empty.
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator. This bit
indicates that the UART is ready to accept a new character for transmission.
In addition, this bit causes the UART to issue an interrupt to CPU when the
THR interrupt enable is set. The THR bit is set to a logic 1 when a character is
transferred from the transmit holding register into the transmitter shift register.
The bit is reset to a logic 0 concurrently with the loading of the transmitter
holding register by the CPU. In the FIFO mode, this bit is set when the
transmit FIFO is empty; it is cleared when at least 1 byte is written to the
transmit FIFO.
LSR[4]
Break interrupt.
Logic 0 = No break condition (normal default condition).
Logic 1 = The receiver received a break signal (RX was a logic 0 for one
character frame time). In the FIFO mode, only one break character is
loaded into the FIFO.
LSR[3]
Framing error.
Logic 0 = No framing error (normal default condition).
Logic 1 = Framing error. The receive character did not have a valid stop
bit(s). In the FIFO mode, this error is associated with the character at the
top of the FIFO.
LSR[2]
Parity error.
Logic 0 = No parity error (normal default condition).
Logic 1 = Parity error. The receive character does not have correct parity
information and is suspect. In the FIFO mode, this error is associated with
the character at the top of the FIFO.
LSR[1]
Overrun error.
Logic 0 = No overrun error (normal default condition).
Logic 1 = Overrun error. A data overrun error occurred in the receive shift
register. This happens when additional data arrives while the FIFO is full. In
this case, the previous data in the shift register is overwritten. Note that
under this condition, the data byte in the receive shift register is not
transferred into the FIFO, therefore the data in the FIFO is not corrupted by
the error.
6
5
4
3
2
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C554B_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs |
| SC16C554BIB64 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C554BIB64,128 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C554BIB64,128 PBF | 制造商:NXP Semiconductors 功能描述: |
| SC16C554BIB64,151 | 功能描述:UART 接口集成電路 4CH. UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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