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參數(shù)資料
| 型號： | SC16C554B |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs |
| 中文描述： | 5伏，3.3伏和2.5伏兆5四異步/秒（最大），16字節(jié)的FIFO |
| 文件頁數(shù)： | 28/51頁 |
| 文件大小： | 253K |
| 代理商： | SC16C554B |
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9397 750 13133
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 9 February 2005
28 of 51
Philips Semiconductors
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 15:
Bit
7
Line Control Register bits description
Symbol
Description
LCR[7]
Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch enabled.
LCR[6]
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic 0.
Logic 0 = no TX break condition (normal default condition).
Logic 1 = forces the transmitter output (TX) to a logic 0 for alerting
the remote receiver to a line break condition.
LCR[5]
Set parity. If the parity bit is enabled, LCR[5] selects the forced parity
format. Programs the parity conditions (see
Table 16
).
Logic 0 = parity is not forced (normal default condition).
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a
logical 1 for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a
logical 0 for the transmit and receive data.
LCR[4]
Even parity. If the parity bit is enabled with LCR[3] set to a logic 1,
LCR[4] selects the even or odd parity format.
Logic 0 = Odd Parity is generated by forcing an odd number of
logic 1s in the transmitted data. The receiver must be programmed
to check the same format (normal default condition).
Logic 1 = Even Parity is generated by forcing an even number of
logic 1s in the transmitted data. The receiver must be programmed
to check the same format.
LCR[3]
Parity enable. Parity or no parity can be selected via this bit.
Logic 0 = no parity (normal default condition).
Logic 1 = a parity bit is generated during the transmission, receiver
checks the data and parity for transmission errors.
LCR[2]
Stop bits. The length of stop bit is specified by this bit in conjunction
with the programmed word length (see
Table 17
).
Logic 0 or cleared = default condition.
LCR[1:0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
Table 18
).
Logic 0 or cleared = default condition.
6
5
4
3
2
1:0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C554B_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs |
| SC16C554BIB64 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C554BIB64,128 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C554BIB64,128 PBF | 制造商:NXP Semiconductors 功能描述: |
| SC16C554BIB64,151 | 功能描述:UART 接口集成電路 4CH. UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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