參數(shù)資料
型號(hào): SC16C2552
廠商: NXP Semiconductors N.V.
英文描述: Dual UART with 16-byte transmit and receive FIFOs
中文描述: 雙UART具有16字節(jié)的傳輸和接收FIFO
文件頁數(shù): 19/38頁
文件大小: 579K
代理商: SC16C2552
Philips Semiconductors
SC16C2552
Dual UART with 16-byte transmit and receive FIFOs
Product data
Rev. 03 — 20 June 2003
19 of 38
9397 750 11636
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 16:
Bit
7-5
4
Modem Control Register bits description
Symbol
Description
MCR[7-5]
Not used; initialized to a logic 0.
MCR[4]
Loop-back. Enable the local loop-back mode (diagnostics). In this
mode the transmitter output TX and the receiver input RX, CTS, DSR,
CD, and RI are disconnected from the SC16C2552 I/O pins.
Internally the modem data and control pins are connected into a
loop-back data configuration (see
Figure 4
). In this mode, the receiver
and transmitter interrupts remain fully operational. The Modem
Control Interrupts are also operational, but the interrupts’ sources are
switched to the lower four bits of the Modem Control. Interrupts
continue to be controlled by the IER register.
Logic 0 = Disable loop-back mode (normal default condition).
Logic 1 = Enable local loop-back mode (diagnostics).
MCR[3]
OP2, INTA/INTB enable. Used to control the modem CD signal in the
loop-back mode.
Logic 0 = Forces INT (A-B) outputs to the 3-State mode and sets
OP2 to a logic 1 (normal default condition). In the loop-back mode,
sets CD internally to a logic 1.
Logic 1 = Forces the INT (A-B outputs to the active mode and sets
OP2 to a logic 0. In the loop-back mode, sets CD internally to a
logic 0.
MCR[2]
OP1. This bit is used in the Loop-back mode only. In the loop-back
mode, this bit is used to write the state of the modem RI interface
signal.
MCR[1]
RTS
Logic 0 = Force RTS output to a logic 1 (normal default condition).
Logic 1 = Force RTS output to a logic 0.
MCR[0]
DTR
Logic 0 = Force DTR output to a logic 1 (normal default condition).
Logic 1 = Force DTR output to a logic 0.
3
2
1
0
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