
100
AMD Geode SC1100 Processor Data Book
SuperI/O Module
Revision 2.0
Index 0Bh
RTC Control Register B - CRB (R/W)
Reset Type: Bit Specific
Width: Byte
7
Set Mode. This bit is reset at VPP power-up reset only.
0: Timing updates occur normally.
1: User copy of time is “frozen”, allowing the time registers to be accessed whether or not an update occurs.
6
Periodic Interrupt. Bits [3:0] of the CRA register determine the rate at which this interrupt is generated. It is cleared to 0 on
RTC reset (i.e., hardware or software reset) or when RTC is disable.
0: Disable.
1: Enable.
5
Alarm Interrupt. This interrupt is generated immediately after a time update in which the seconds, minutes, hours, date and
month time equal their respective alarm counterparts. It is cleared to 0 as long as bit 7 of the CRD register reads 0.
0: Disable.
1: Enable.
4
Update Ended Interrupt. This interrupt is generated when an update occurs. It is cleared to 0 on RTC reset (i.e., hardware
or software reset) or when the RTC is disable.
0: Disable.
1: Enable.
3
Reserved. This bit is defined as “Square Wave Enable” by the MC146818 and is not supported by the RTC. This bit is
always read as 0.
2
Data Mode. This bit is reset at VPP power-up reset only.
0: Enable BCD format.
1: Enable Binary format.
1
Hour Mode. This bit is reset at VPP power-up reset only.
0: Enable 12-hour format.
1: Enable 24-hour format.
0
Daylight Saving. This bit is reset at VPP power-up reset only.
0: Disable.
1: Enable:
- In the spring, time advances from1:59:59 AM to 3:00:00 AM on the first Sunday in April.
- In the fall, time returns from 1:59:59 AM to 1:00:00 AM on the last Sunday in October.
Index 0Ch
RTC Control Register C - CRC (RO)
Reset Type: Bit Specific
Width: Byte
7
IRQ Flag. Mirrors the value on the interrupt output signal. When interrupt is active, IRQF is 1. To clear this bit (and deacti-
vate the interrupt pin), read the CRC register as the flag bits UF, AF and PF are cleared after reading this register.
0: IRQ inactive.
1: Logic equation is true: ((UIE and UF) or (AIE and AF) or (PIE and PF)).
6
Periodic Interrupt Flag. Cleared to 0 on RTC reset (i.e., hardware or software reset) or the RTC disabled. In addition, this
bit is cleared to 0 when this register is read.
0: No transition occurred on the selected tap since the last read.
1: Transition occurred on the selected tap of the divider chain.
5
Alarm Interrupt Flag. Cleared to 0 as long as bit 7 of the CRD register reads 0. In addition, this bit is cleared to 0 when this
register is read.
0: No alarm detected since the last read.
1: Alarm condition detected.
4
Update Ended Interrupt Flag. Cleared to 0 on RTC reset (i.e., hardware or software reset) or the RTC disabled. In addition,
this bit is cleared to 0 when this register is read.
0: No update occurred since the last read.
1: Time registers updated.
3:0
Reserved.
Table 5-18. RTC Registers (Continued)
Bit
Description