參數(shù)資料
型號(hào)： SB83C196KD
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝： SQFP-80
文件頁(yè)數(shù)： 5/25頁(yè)
文件大?。?/td> 1691K
代理商： SB83C196KD
8XC196KD/8XC196KD20
AC CHARACTERISTICS (Continued)
For use over specified operating conditions.
Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16/20 MHz
The 80C196KD will meet these specifications:
Symbol
Description
Min
Max
Units
Notes
FXTAL
Frequency on XTAL1 (8XC196KD)
8
16
MHz
(Note 1)
FXTAL
Frequency on XTAL1 (8XC196KD20)
8
20
MHz
(Note 1)
TOSC
I/F XTAL (8XC196KD)
62.5
125
ns
TOSC
I/F XTAL (8XC196KD20)
50
125
ns
TXHCH
XTAL1 High to CLKOUT High or Low
a
20
a
110
ns
TCLCL
CLKOUT Cycle Time
2 TOSC
ns
TCHCL
CLKOUT High Period
TOSC b 10
TOSCa15
ns
TCLLH
CLKOUT Falling Edge to ALE Rising
b
5
a
15
ns
TLLCH
ALE Falling Edge to CLKOUT Rising
b
20
a
15
ns
TLHLH
ALE Cycle Time
4 TOSC
ns
(Note 4)
TLHLL
ALE High Period
TOSC b 10
TOSCa10
ns
TAVLL
Address Setup to ALE Falling Edge
TOSC b 15
TLLAX
Address Hold after ALE Falling Edge
TOSC b 35
ns
TLLRL
ALE Falling Edge to RD Falling Edge
TOSC b 30
ns
TRLCL
RD Low to CLKOUT Falling Edge
a
4
a
30
ns
TRLRH
RD Low Period
TOSC b 5
ns
(Note 4)
TRHLH
RD Rising Edge to ALE Rising Edge
TOSC
TOSC a 25
ns
(Note 2)
TRLAZ
RD Low to Address Float
a
5ns
TLLWL
ALE Falling Edge to WR Falling Edge
TOSC b 10
ns
TCLWL
CLKOUT Low to WR Falling Edge
0
a
25
ns
TQVWH
Data Stable to WR Rising Edge
TOSC b 23
(Note 4)
TCHWH
CLKOUT High to WR Rising Edge
b
5
a
15
ns
TWLWH
WR Low Period
TOSC b 20
ns
(Note 4)
TWHQX
Data Hold after WR Rising Edge
TOSC b 25
ns
TWHLH
WR Rising Edge to ALE Rising Edge
TOSC b 10
TOSC a 15
ns
(Note 2)
TWHBX
BHE, INST after WR Rising Edge
TOSC b 10
ns
TWHAX
AD8±15 HOLD after WR Rising
TOSC b 30
ns
(Note 3)
TRHBX
BHE, INST after RD Rising Edge
TOSC b 10
ns
TRHAX
AD8±15 HOLD after RD Rising
TOSC b 25
ns
(Note 3)
NOTES:
1. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Assuming back-to-back bus cycles.
3. 8-Bit bus only.
4. If wait states are used, add 2 TOSC N, where N e number of wait states.
13
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