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| 型號(hào)： | SAX-XC878M-13FFI5V |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 24 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, TQFP-64 |
| 文件頁(yè)數(shù)： | 135/141頁(yè) |
| 文件大?。?/td> | 2385K |
| 代理商： | SAX-XC878M-13FFI5V |
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XC878CLM
Functional Description
Data Sheet
86
V1.1, 2009-08
fractional divider) for generating a wide range of baud rates based on its input clock
f
PCLK,
see Figure 25.
Figure 25
Baud-rate Generator Circuitry
The baud rate timer is a count-down timer and is clocked by either the output of the
fractional divider (
f
MOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the
output of the prescaler (
f
DIV) if the fractional divider is disabled (FDEN = 0). For baud rate
generation, the fractional divider must be configured to fractional divider mode
(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start
or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit
reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the
baud rate timer and nullifies the effect of bit BCON.R. See Section 3.14.
The baud rate (
f
BR) value is dependent on the following parameters:
Input clock
f
PCLK
Prescaling factor (2BRPRE) defined by bit field BRPRE in register BCON
Fractional divider (STEP/256) defined by register FDSTEP
(to be considered only if fractional divider is enabled and operating in fractional
divider mode)
8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG
FDSTEP
1
FDM
Adder
FDRES
FDEN&FDM
clk
Fractional Divider
Prescaler
NDOV
‘0’
FDEN
00
01
10
11
10
01
00
0
1
(overflow)
0
f
BR
8-Bit Baud Rate Timer
8-Bit Reload Value
R
0
1
f
DIV
f
DIV
fPCLK
f
MOD
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