
XC878CLM
Functional Description
Data Sheet
100
V1.1, 2009-08
3.22
Analog-to-Digital Converter
The XC878 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with
eight multiplexed analog input channels. The ADC uses a successive approximation
technique to convert the analog voltage levels from up to eight different sources. The
analog input channels of the ADC are available at AN0 - AN7.
Features
Successive approximation
8-bit or 10-bit resolution
Eight analog channels
Four independent result registers
Result data protection for slow CPU access
(wait-for-read mode)
Single conversion mode
Autoscan functionality
Limit checking for conversion results
Data reduction filter
(accumulation of up to 2 conversion results)
Two independent conversion request sources with programmable priority
Selectable conversion request trigger
Flexible interrupt generation with configurable service nodes
Programmable sample time
Programmable clock divider
Cancel/restart feature for running conversions
Integrated sample and hold circuitry
Compensation of offset errors
Low power modes
3.22.1
ADC Clocking Scheme
A common module clock
f
ADC generates the various clock signals used by the analog and
digital parts of the ADC module:
f
ADCA is input clock for the analog part.
f
ADCI is internal clock for the analog part (defines the time base for conversion length
and the sample time). This clock is generated internally in the analog part, based on
the input clock
f
ADCA to generate a correct duty cycle for the analog components.
f
ADCD is input clock for the digital part.
Figure 30 shows the clocking scheme of the ADC module. The prescaler ratio is
selected by bit field CTC in register GLOBCTR. A prescaling ratio of 32 can be selected
when the maximum performance of the ADC is not required.