參數(shù)資料
型號: SAL-XC886C-6FFA5V
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP48
封裝: GREEN, PLASTIC, TQFP-48
文件頁數(shù): 89/134頁
文件大?。?/td> 864K
代理商: SAL-XC886C-6FFA5V
SAL-XC886CLM
Functional Description
Data Sheet
51
V1.0, 2010-05
Figure 10
Flash Bank Sectorization
The internal structure of each Flash bank represents a sector architecture for flexible
erase capability. The minimum erase width is always a complete sector, and sectors can
be erased separately or in parallel. Contrary to standard EPROMs, erased Flash
memory cells contain 0s.
The D-Flash bank is divided into more physical sectors for extended erasing and
reprogramming capability; even numbers for each sector size are provided to allow
greater flexibility and the ability to adapt to a wide range of application requirements.
3.3.2
Parallel Read Access of P-Flash
To enhance system performance, the P-Flash banks are configured for parallel read to
allow two bytes of linear code to be read in 4 x CCLK cycles, compared to 6 x CCLK
cycles if serial read is performed. This is achieved by reading two bytes in parallel from
a P-Flash bank pair within the 3 x CCLK cycles access time and storing them in a cache.
Subsequent read from the cache by the CPU does not require a wait state and can be
completed within 1 x CCLK cycle. The result is the average instruction fetch time from
the P-Flash banks is reduced and thus, the MIPS (Mega Instruction Per Second) of the
system is increased.
However, if the parallel read feature is not desired due to certain timing constraints, it can
be disabled by calling the parallel read disable subroutine.
Sector 9: 128-byte
Sector 5: 256-byte
Sector 3: 512-byte
Sector 1: 1-Kbyte
Sector 0: 1-Kbyte
Sector 7: 128-byte
Sector 8: 128-byte
Sector 6: 128-byte
Sector 4: 256-byte
Sector 2: 512-byte
Sector 0: 3.75-Kbyte
P-Flash
D-Flash
Sector 2: 128-byte
Sector 1: 128-byte
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