參數(shù)資料
型號: SAL-XC886C-6FFA5V
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP48
封裝: GREEN, PLASTIC, TQFP-48
文件頁數(shù): 106/134頁
文件大?。?/td> 864K
代理商: SAL-XC886C-6FFA5V
SAL-XC886CLM
Functional Description
Data Sheet
66
V1.0, 2010-05
3.7
Reset Control
The SAL-XC886 has five types of reset: power-on reset, hardware reset, watchdog timer
reset, power-down wake-up reset, and brownout reset.
When the SAL-XC886 is first powered up, the status of certain pins (see Table 22) must
be defined to ensure proper start operation of the device. At the end of a reset sequence,
the sampled values are latched to select the desired boot option, which cannot be
modified until the next power-on reset or hardware reset. This guarantees stable
conditions during the normal operation of the device.
In order to power up the system properly, the external reset pin RESET must be asserted
until
V
DDC reaches 0.9*VDDC. The delay of external reset can be realized by an external
capacitor at RESET pin. This capacitor value must be selected so that
V
RESET reaches
0.4 V, but not before
V
DDC reaches 0.9* VDDC.
A typical application example is shown in Figure 21. The
V
DDP capacitor value is 100 nF
while the
V
DDC capacitor value is 220 nF. The capacitor connected to RESET pin is
100 nF.
Typically, the time taken for
V
DDC to reach 0.9*VDDC is less than 50 s once VDDP reaches
2.3V. Hence, based on the condition that 10% to 90%
V
DDP (slew rate) is less than
500
s, the RESET pin should be held low for 500 s typically. See Figure 22.
Figure 21
Reset Circuitry
VSSP
VDDP
VDDC
VSSC
5V
RESET
EVR
VR
VIN
100nF
220nF
typ.
100nF
XC886
30k
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