參數(shù)資料
型號: SAK-TC1767-256F133HL
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 133 MHz, RISC MICROCONTROLLER, PQFP176
封裝: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-176
文件頁數(shù): 12/126頁
文件大?。?/td> 826K
代理商: SAK-TC1767-256F133HL
TC1767
Electrical Parameters
Data Sheet
105
V1.3, 2009-09
Figure 25
Power, Pad and Reset Timing
2)
t
OSCS is defined from the moment when VDDOSC3 = 3.13 V until the oscillations reach an amplitude at XTAL1 of
0,3
× V
DDOSC3. This parameter is verified by device characterization. The external oscillator circuitry must be
optimized by the customer and checked for negative resistance as recommended and specified by crystal
suppliers.
3) Any ESR0 activation is internally prolonged to SCU_RSTCNTCON.RELSA FPI bus clock (
f
FPI) cycles.
4) Applicable for input pins TESTMODE and TRST.
5)
f
FPI = fCPU /2
6) Not subject to production test, verified by design / characterization.
7) This parameter includes the delay of the analog spike filter in the PORST pad.
8) The duration of the boot-time is defined between the rising edge of the PORST and the moment when the first
user instruction has entered the CPU and its processing starts.
9) The duration of the boot time is defined between the rising edge of the internal application reset and the clock
cycle when the first user instruction has entered the CPU pipeline and its processing starts.
10) The given time includes the time of the internal reset extension for a configured value of
SCU_RSTCNTCON.RELSA = 0x05BE.
reset_beh2
As programmed
VDDP
Pads
Pad-state undefined
VDD
VDDPPA
t hd
tPOA
TRST
TESTMODE
ESR0
PORST
tPOH
HWCFG
tHDH
t PIP
tPI
Tri-state or pull device active
t hd
tPOH
tHDH
t PIP
tPI
t PIP
tPI
tHDH
tPI
VDDP -12%
VDD -12%
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