參數(shù)資料
型號： SAH-XC2723X-20F66V
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PQCC48
封裝： 0.50 MM PITCH, GREEN, PLASTIC, VQFN-48
文件頁數(shù)： 38/112頁
文件大?。?/td> 3116K
代理商： SAH-XC2723X-20F66V
XC2723X
XC2000 Family / Econo Line
Functional Description
PRELIMINARY
Data Sheet
27
V1.0, 2010-12
This common memory space consists of 16 Mbytes organized as 256 segments of
64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory
space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the
register spaces (ESFR/SFR) additionally are directly bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
access to the program memories such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
access to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected to the high-speed system bus so that they can
exchange data. This is required if operands are read from program memory, code or
data is written to the PSRAM, code is fetched from external memory, or data is read from
or written to external resources. These include peripherals on the LXBus such as USIC
or MultiCAN. The system bus allows concurrent two-way communication for maximum
transfer performance.
4 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.
The PSRAM is accessed via the PMU and is optimized for code fetches. A section of the
PSRAM with programmable size can be write-protected.
ESFR area
00’F000H 00’F1FFH 0.5 Kbytes
XSFR area
00’E000H 00’EFFFH 4 Kbytes
Data SRAM (DSRAM)
00’C800H 00’DFFFH 6 Kbytes
Reserved for DSRAM
00’8000H 00’C7FFH 18 Kbytes
External memory area
00’0000H 00’7FFFH 32 Kbytes
1) Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate
external bus accesses.
2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
3) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH).
4) Several pipeline optimizations are not active within the external IO area.
Table 8
XC2723X Memory Map (cont’d)1) (cont’d)
Address Area
Start Loc. End Loc.
Area Size2)
Notes
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