參數(shù)資料
型號: SAF-C161O-LM3VHA
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 20 MHz, MICROCONTROLLER, PQFP80
封裝: 0.65 MM PITCH, ROHS COMPLIANT, PLASTIC, MQFP-80
文件頁數(shù): 57/68頁
文件大?。?/td> 1121K
代理商: SAF-C161O-LM3VHA
C161K
C161O
Data Sheet
56
V2.0, 2001-01
Data float after RdCS
(with RW-delay)1)
t53 SR –
30 +
tF
2TCL - 20
+ 2
tA + tF
ns
Data float after RdCS
(no RW-delay)1)
t68 SR –
5 +
tF
TCL - 20
+ 2
tA + tF
ns
Address hold after
RdCS, WrCS
t55 CC -16 + tF
-16 +
tF
ns
Data hold after WrCS
t57 CC 9 + tF
TCL - 16
+
tF
ns
1) RW-delay and t
A refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1 / 2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
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