參數(shù)資料
型號： SAF-C161O-LM3VHA
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 20 MHz, MICROCONTROLLER, PQFP80
封裝： 0.65 MM PITCH, ROHS COMPLIANT, PLASTIC, MQFP-80
文件頁數(shù)： 44/68頁
文件大?。?/td> 1121K
代理商： SAF-C161O-LM3VHA
C161K
C161O
Data Sheet
45
V2.0, 2001-01
Data float after RD
t19 SR –
36 +
tF
–
2TCL - 14
+
tF
ns
Data valid to WR
t22 CC 24 + tC
–
2TCL - 26
+
tC
–
ns
Data hold after WR
t23 CC 36 + tF
–
2TCL - 14
+
tF
–
ns
ALE rising edge after RD,
WR
t25 CC 36 + tF
–
2TCL - 14
+
tF
–
ns
Address hold after RD,
WR
t27 CC 36 + tF
–
2TCL - 14
+
tF
–
ns
ALE falling edge to CS1)
t38 CC -8 - tA
10 -
tA
-8 -
tA
10 -
tA
ns
CS low to Valid Data In1)
t39 SR –
47+
tC
+ 2
tA
–
3TCL - 28
+
tC + 2tA
ns
CS hold after RD, WR1)
t40 CC 57 + tF
–
3TCL - 18
+
tF
–
ns
ALE fall. edge to RdCS,
WrCS (with RW delay)
t42 CC 19 + tA
–
TCL - 6
+
tA
–
ns
ALE fall. edge to RdCS,
WrCS (no RW delay)
t43 CC -6 + tA
–
-6
+
tA
–
ns
Address float after RdCS,
WrCS (with RW delay)
t44 CC –
0
–
0ns
Address float after RdCS,
WrCS (no RW delay)
t45 CC –
25
–
TCL
ns
RdCS to Valid Data In
(with RW delay)
t46 SR –
20 +
tC
–
2TCL - 30
+
tC
ns
RdCS to Valid Data In
(no RW delay)
t47 SR –
45 +
tC
–
3TCL - 30
+
tC
ns
RdCS, WrCS Low Time
(with RW delay)
t48 CC 38 + tC
–
2TCL - 12
+
tC
–
ns
RdCS, WrCS Low Time
(no RW delay)
t49 CC 63 + tC
–
3TCL - 12
+
tC
–
ns
Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1 / 2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
相關(guān)PDF資料
PDF描述
SAF-C161RI-LM 16-BIT, 20 MHz, MICROCONTROLLER, PQFP100
SAB-C161RI-LF 16-BIT, 20 MHz, MICROCONTROLLER, PQFP100
SAF-C161S-L25M 16-BIT, 25 MHz, MICROCONTROLLER, PQFP80
SAB-C161S-LM3V 16-BIT, 20 MHz, MICROCONTROLLER, PQFP80
SAB-C161S-L25M 16-BIT, 25 MHz, MICROCONTROLLER, PQFP80
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