參數(shù)資料
型號: SAF-C161O-LM3VHA
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 20 MHz, MICROCONTROLLER, PQFP80
封裝: 0.65 MM PITCH, ROHS COMPLIANT, PLASTIC, MQFP-80
文件頁數(shù): 42/68頁
文件大?。?/td> 1121K
代理商: SAF-C161O-LM3VHA
C161K
C161O
Data Sheet
43
V2.0, 2001-01
Address float after RdCS,
WrCS (with RW delay)
t44 CC –
0
0ns
Address float after RdCS,
WrCS (no RW delay)
t45 CC –
20
TCL
ns
RdCS to Valid Data In
(with RW delay)
t46 SR –
16 +
tC
2TCL - 24
+
tC
ns
RdCS to Valid Data In
(no RW delay)
t47 SR –
36 +
tC
3TCL - 24
+
tC
ns
RdCS, WrCS Low Time
(with RW delay)
t48 CC 30 + tC
2TCL - 10
+
tC
ns
RdCS, WrCS Low Time
(no RW delay)
t49 CC 50 + tC
3TCL - 10
+
tC
ns
Data valid to WrCS
t50 CC 26 + tC
2TCL - 14
+
tC
ns
Data hold after RdCS
t51 SR 0
0
ns
Data float after RdCS
t52 SR –
20 +
tF
2TCL - 20
+
tF
ns
Address hold after
RdCS, WrCS
t54 CC 20 + tF
2TCL - 20
+
tF
ns
Data hold after WrCS
t56 CC 20 + tF
2TCL - 20
+
tF
ns
1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Multiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
min.
max.
min.
max.
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