參數(shù)資料
型號： SAF-C161O-LM3VHA
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 20 MHz, MICROCONTROLLER, PQFP80
封裝： 0.65 MM PITCH, ROHS COMPLIANT, PLASTIC, MQFP-80
文件頁數(shù)： 41/68頁
文件大?。?/td> 1121K
代理商： SAF-C161O-LM3VHA
C161K
C161O
Data Sheet
42
V2.0, 2001-01
RD, WR low time
(no RW-delay)
t13 CC 50 + tC
–
3TCL - 10
+
tC
–
ns
RD to valid data in
(with RW-delay)
t14 SR –
20 +
tC
–
2TCL - 20
+
tC
ns
RD to valid data in
(no RW-delay)
t15 SR –
40 +
tC
–
3TCL - 20
+
tC
ns
ALE low to valid data in
t16 SR –
40 +
tA
+
tC
–
3TCL - 20
+
tA + tC
ns
Address to valid data in
t17 SR –
50 + 2
tA
+
tC
–
4TCL - 30
+ 2
tA + tC
ns
Data hold after RD
rising edge
t18 SR 0
–
0
–
ns
Data float after RD
t19 SR –
26 +
tF
–
2TCL - 14
+
tF
ns
Data valid to WR
t22 CC 20 + tC
–
2TCL - 20
+
tC
–
ns
Data hold after WR
t23 CC 26 + tF
–
2TCL - 14
+
tF
–
ns
ALE rising edge after RD,
WR
t25 CC 26 + tF
–
2TCL - 14
+
tF
–
ns
Address hold after RD,
WR
t27 CC 26 + tF
–
2TCL - 14
+
tF
–
ns
ALE falling edge to CS1)
t38 CC -4 - tA
10 -
tA
-4 -
tA
10 -
tA
ns
CS low to Valid Data In1)
t39 SR –
40 +
tC
+ 2
tA
–
3TCL - 20
+
tC + 2tA
ns
CS hold after RD, WR1)
t40 CC 46 + tF
–
3TCL - 14
+
tF
–
ns
ALE fall. edge to RdCS,
WrCS (with RW delay)
t42 CC 16 + tA
–
TCL - 4
+
tA
–
ns
ALE fall. edge to RdCS,
WrCS (no RW delay)
t43 CC -4 + tA
–
-4
+
tA
–
ns
Multiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
min.
max.
min.
max.
相關(guān)PDF資料
PDF描述
SAF-C161RI-LM 16-BIT, 20 MHz, MICROCONTROLLER, PQFP100
SAB-C161RI-LF 16-BIT, 20 MHz, MICROCONTROLLER, PQFP100
SAF-C161S-L25M 16-BIT, 25 MHz, MICROCONTROLLER, PQFP80
SAB-C161S-LM3V 16-BIT, 20 MHz, MICROCONTROLLER, PQFP80
SAB-C161S-L25M 16-BIT, 25 MHz, MICROCONTROLLER, PQFP80
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