參數(shù)資料
型號: SAB-C161S-LM3V
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 20 MHz, MICROCONTROLLER, PQFP80
封裝: PLASTIC, MQFP-80
文件頁數(shù): 63/75頁
文件大?。?/td> 1315K
代理商: SAB-C161S-LM3V
C161S
Timing Characteristics
Data Sheet
62
V1.0, 2003-11
Data float after RdCS
(no RW-delay)
t
68
SR –
0 +
t
F
TCL - 20
+ 2
t
A + tF
ns
Address hold after
RdCS, WrCS
t
55
CC -6 +
t
F
-6 +
t
F
ns
Data hold after WrCS
t
57
CC 6 +
t
F
TCL - 14
+
t
F
ns
1) RW-delay and
t
A refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Table 18
Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
t
A + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
Min.
Max.
Min.
Max.
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