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| 型號： | SAB-C161S-LM3V |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 20 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, MQFP-80 |
| 文件頁數(shù)： | 14/75頁 |
| 文件大?。?/td> | 1315K |
| 代理商： | SAB-C161S-LM3V |
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C161S
Functional Description
Data Sheet
17
V1.0, 2003-11
The C161S also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurrence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.
Table 4 shows all of the possible exceptions or error conditions that can arise during run-
time:
Table 4
Hardware Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Location
Trap
Number
Trap
Priority
Reset Functions:
Hardware Reset
Software Reset
W-dog Timer Overflow
–
RESET
00’0000
H
00’0000
H
00’0000
H
00
H
00
H
00
H
III
Class A Hardware Traps:
Non-Maskable
Interrupt
Stack Overflow
Stack Underflow
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
00’0008
H
00’0010
H
00’0018
H
02
H
04
H
06
H
II
Class B Hardware Traps:
Undefined Opcode
Protected Instruction
Fault
Illegal Word Operand
Access
Illegal Instruction
Access
Illegal External Bus
Access
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
00’0028
H
00’0028
H
00’0028
H
00’0028
H
00’0028
H
0A
H
0A
H
0A
H
0A
H
0A
H
I
Reserved
–
[2C
H –
3C
H]
[0B
H –
0F
H]
–
Software Traps
TRAP Instruction
––
Any
[00’0000
H –
00’01FC
H]
in steps of
4
H
Any
[00
H –
7F
H]
Current
CPU
Priority
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