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| 型號(hào)： | SAB-C161S-LM3V |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 20 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, MQFP-80 |
| 文件頁(yè)數(shù)： | 48/75頁(yè) |
| 文件大?。?/td> | 1315K |
| 代理商： | SAB-C161S-LM3V |
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C161S
Timing Characteristics
Data Sheet
48
V1.0, 2003-11
5.2
External Clock Drive XTAL1
Figure 12
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is
limited to a range of 4 MHz to 16 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is verified by design
only (not tested in production).
Table 14
External Clock Drive XTAL1 (Operating Conditions apply)
Parameter
Symbol
Direct Drive
1:1
Prescaler
2:1
PLL
1:N
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Oscillator
period
t
OSC
SR
40
–
20
–
60
1)
1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock
generation mode. Please see respective table above.
500
ns
High time
2)
2) The clock input signal must reach the defined levels
V
IL2 and VIH2.
t
1
SR
20
3)
3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (
f
CPU) in
direct drive mode depends on the duty cycle of the clock input signal.
–
5
–
10
–
ns
Low time
t
2
SR
20
–
5
–
10
–
ns
Rise time
t
3
SR
–
8
–
5
–
10
ns
Fall time
t
4
SR
–
8
–
5
–
10
ns
MCT02534
3
t
4
t
VIH2
VIL
V
DD
0.5
1
t
2
t
OSC
t
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