參數(shù)資料
型號(hào): SAA8110G
廠商: NXP SEMICONDUCTORS
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processor (DSP) for cameras(應(yīng)用于照相中的數(shù)字信號(hào)處理器)
中文描述: 0-BIT, 28.6 MHz, OTHER DSP, PQFP80
封裝: 12 X 12 X 1.40 MM, PLASTIC, LQFP-80
文件頁數(shù): 18/36頁
文件大?。?/td> 232K
代理商: SAA8110G
1997 Jun 13
18
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
Notes
1.
2.
3.
When CVBS output is used the chrominance range is halved compared to luminance.
Monitor load of 75
with R
ext
= 21
and R
bias
= 15 k
at 3.3 V application.
Monitor load of 75
with R
ext
= 70.6
and R
bias
= 47 k
at 5.0 V application.
CDAC specification (V
DD
= 5 V)
L
int
L
diff
V
o(CDAC)
integral linearity
differential linearity
output voltage at pin CDAC
4.6
3
10
4.95
3.25
13
28.6
10
1
1
2
300
10
104
LSB
LSB
mV
V
V
MHz
k
pF
ns
code 0
code 61, V
DDA
= 5 V
code 61, V
DDA
= 3.3 V
R
o(CDAC)
f
clk
R
L
C
L
t
PD
output resistance at pin CDAC
clock frequency
load resistance
load capacitance
propagation delay time
to 50% value (see Fig.17),
V
DDA
= 5 V
10% to 90% full-scale (see
Fig.16)
to
±
1 LSB (see Fig.16)
t
st(10-90)
settling time
9
ns
t
st(LSB)
I
NPUTS RELATED TO
CLK1: CCD0
TO
CCD9, VSYNC
IN
, HSYNC
IN,
FI
IN
t
su(i)(D)1
data input set-up time CCD
inputs, HSYNC
IN
, VSYNC
IN
, FI
IN
t
su(i)(D)2
data input set-up time SN
RES
and
SN
DA
t
h(i)(CCD)
data hold time CCD inputs
t
h(i)(D)
data input hold time
O
UTPUTS RELATED TO
CLK2: Y7
TO
Y0, UV7
TO
UV0, CREF, HREF, VSYNC
OUT
, FI
OUT
AND
LLC
t
h(o)(D)
data output hold time
t
d(o)(D)
data output delay time
O
UTPUTS RELATED TO
CLK1: SDATA, STROBE, SMP, P0, P1
AND
SCLK
setting time
25
ns
0
3
5
ns
0
1
2
ns
1
0
1
+1
3
ns
ns
VSYNC
IN
, HSYNC
IN
, FI
IN
8
25
22
31
ns
ns
t
h(o)(D)
t
d(o)(D)
δ
clk
data output hold time
data output delay time
clock duty cycle
40
13
15
21
24
60
ns
ns
%
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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