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參數(shù)資料
| 型號： | SAA8110G |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processor (DSP) for cameras(應(yīng)用于照相中的數(shù)字信號處理器) |
| 中文描述： | 0-BIT, 28.6 MHz, OTHER DSP, PQFP80 |
| 封裝： | 12 X 12 X 1.40 MM, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 15/36頁 |
| 文件大?。?/td> | 232K |
| 代理商： | SAA8110G |
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1997 Jun 13
15
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
Analog output preprocessing
This block contains several features:
Delay compensation for the luminance signal
Up-sampling of the UV signal
PAL/NTSC encoding
YUV to RGB conversion
Selection of the required analog output format (RGB,
YUV, YC or CVBS).
The analog outputs are given by three voltage DACs in
RGB or YUV or CVBS or YC format. Channels Y and G
include the sync information. Over-sampling at twice f
clk
is
made so that external filtering becomes easier. It is also
possible to have an adjustment of the subcarrier via the
serial interface. When CVBS output is used, chrominance
range is halved compared to luminance.
Measurement engine
The measurement engine performs measurements on
some selectable internal signals on frame/field basis and
prepares data for auto exposure, auto focus and auto
white balance processing. It uses an internal RAM
work-space for its control and data handling operations.
The contents of the work-space can be accessed via the
serial interface.
Vertical/horizontal reference and window timing and
control
The SAA8110G uses two vertical and horizontal
synchronization input signals (VSYNC
IN
and HSYNC
IN
) to
derive internal vertical and horizontal reference signals.
Besides a Field Identification input (FI
IN
) signal is required.
The timing of the vertical and horizontal input signals
should be such that:
1.
The pixel frequency (CLK1) must be line-locked to the
line frequency of HSYNC
IN
: the number of clock
periods between two HSYNC
IN
pulses must be a fixed
integer number. The HSYNC
IN
should be at least one
clock period active HIGH.
2.
The VSYNC
IN
signal indicates the start of a field
(
or frame in case of progressive scanning
); this
signal is also required for non-interlaced applications.
The VSYNC
IN
should be at least one clock period
HIGH.
3.
The FI
IN
pulse indicates the phase of the field in case
of interlaced applications (FI
IN
= 0 means odd field).
Serial interface
The serial interface can either be an I
2
C-bus or a 80C51
UART (SNERT) (selectable with the SIS pin). Via the serial
interface the external microcontroller can control the
internal settings of the SAA8110G and read/write from/to
the internal RAM work-space linked to the measurement
engine (see list of parameter settings in
Chapter “Programming”). Some of the registers are
double-buffered to prevent that the change of control data
becomes visible on the output display.
Miscellaneous functions
A three wire bus is used to send 10-bit settings from a
microcontroller to the TDA8786 via the SAA8110G
registers.The SAA8110G supplies picture parameters and
needs some configuration parameters. Those values are
contained in registers and are updated during every
vertical synchronization pulse.
Mode control
This block controls the operation mode of the SAA8110G.
As described in Table 2, four modes may be selected:
depending on power reduction and I
2
C-bus timing.
Power dissipation management
The power dissipation of the SAA8110G will depend on the
required activity for a certain application. It is possible to
switch off via the serial interface unconcerned parts for a
given application. When an analog output is not used, the
power voltage pin of the DAC can be connected to ground
to limit the power consumption.
Clock configurations
Following conditions must be fulfilled:
CLK1 should be generated as divide-by-two from CLK2
The RESET pin should not go LOW before CLK1 and
CLK2 are both HIGH or LOW.
Table 2
SAA8110G mode control
T2
T1
T0
MODE
POWER
REDUCTION
t
o(h)
I
2
C-BUS
0
0
0
0
0
0
1
1
0
1
0
1
application
mode
on
on
off
off
short
long
short
long
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA8122A | Digital Still Camera Processor (ImagIC family)(數(shù)字靜態(tài)照相處理器) |
| SAA8122AEL | Digital Still Camera Processor ImagIC family |
| SAB-C504-2R24M | 8-Bit CMOS Microcontroller |
| SAB-C504-2R40M | 8-Bit CMOS Microcontroller |
| SAB-C504-2RM | 8-Bit CMOS Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA8112HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital camera signal processor and microcontroller |
| SAA8113HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital PC-camera signal processor |
| SAA8115HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital camera USB interface |
| SAA8116 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital PC-camera signal processor including microcontroller and USB interface |
| SAA8116104BE | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC PC WEB CAMERA DSP WITH USB RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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