參數(shù)資料
型號(hào)： SAA7708H
廠(chǎng)商： NXP Semiconductors N.V.
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： Car Radio Digital Signal Processor
中文描述： 汽車(chē)無(wú)線(xiàn)電數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 29/60頁(yè)
文件大?。?/td> 281K
代理商： SAA7708H
1998 May 19
29
Philips Semiconductors
Preliminary specification
Car Radio Digital Signal Processor
SAA7708H
10.14.4 G
ENERAL DESCRIPTION
SPDIF INPUTS
For communication with external digital sources also a SPDIF input can be used. The two SPDIF input pins can be
connected via an analog multiplexer to the SPDIF receiver. It is a receiver without an analogue PLL that samples the
incoming SPDIF with a high frequency. In this way the data is recovered synchronously on the applied system clock. Also
a 64*Fs clock is regenerated out of the SPDIF datastream.
From the SPDIF signal a three wire (I2S like) serial bus is made, consisting of a Wordselect, Data and Bitclock line. The
FS frequency depends solely on the SPDIF signal input accuracy.
This design does NOT handle the userdata-, channelstatus- and validitybits of the SPDIF stream, but only the audio is
given at its outputs. The bits in the audio space are always decoded regardless of any statusbits e.g. ’copy protected’,
’professional mode’ or ’data mode’.
10.14.4.1 SPDIF format
The SPDIF format used here carries the 2 channel PCM audio over a two wire pair.
The SPDIF format can be partitioned into two main layers, being the abstract model of frames and blocks, and the
channel modulation. Currently there are three samples frequencies specified:
Table 5
Sample Frequencies
10.14.4.2 SPDIF channel modulation
The digital signal is coded using “biphase-mark-code” (BMC), which is a kind of phase-modulation. In this scheme, a
logic one in the data corresponds to two zero-crossings in the coded signal, and a logic zero to one zero-crossing
The SPDIF interface of the SAA7708 is capable of decoding all standardized sampling frequencies with Level3 timing
being the whole range of 28 kHz to 54 kHz sampling frequency. However the highest frequency posible is in fact due to
the limited cycle budget of the DSP only 44.1 kHz.
SAMPLE FREQ [KHZ]
DATA-RATE [MBIT/S]
CHANNEL-RATE [MBIT/S]
44.1
48.0
32.0
2.8224
3.072
2.048
5.6448
6.144
4.096
Clock
Data
BMC
Fig. 12 BiPhase Mark Coding
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參數(shù)描述
SAA7709/N107 制造商:PHILIPS-SEMI 功能描述:
SAA7709H/N103 功能描述:音頻 DSP DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
SAA7709H/N103,518 功能描述:音頻 DSP DIRAC-2 RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
SAA7709H/N103,557 功能描述:音頻 DSP DIGITAL SIGNAL RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
SAA7709H/N103/S420 功能描述:音頻 DSP Car radio Digital Signal Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
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