參數(shù)資料
型號(hào)： SAA7348GP
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： All Compact Disc Engine ACE
中文描述： 8-BIT, MROM, 35 MHz, MICROCONTROLLER, PQFP100
文件頁(yè)數(shù)： 28/60頁(yè)
文件大?。?/td> 205K
代理商： SAA7348GP
1997 Jul 11
28
Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
8.1.5
M
OTOR
O
UTPUT
QCLV R
EGISTER
(MOQ; address 0XF2H and 0XF3H)
The Motor Output QCLV register holds the sixteen bits of the filtered (
3 dB, 300 Hz) motor error signal. This signal is
updated at a frequency of 16.537 kHz. Address 0XF3H holds the eight most significant bits, address 0XF2H the eight
least significant bits. Refreshing rule: if the low byte is read, the high byte is locked to avoid mixing up two successive
samples. If the high byte has been read, the low byte will be refreshed. The register is byte addressable; read only.
8.1.6
P3 R
EGISTER
The P3 register is used in the same way as in the standard 80C51. It contains a second UART, however, whose input
and output pins are R
XD1
and T
XD1
respectively. Direction control is by DDROUT3 (SFR address 0XFD; see Table 25
and Section 8.1.12). The register is bit addressable; R/W.
Table 18
P3 register (address 0XB0H to 0XB7H)
Table 19
Description of P3 register bits
7
6
5
4
3
2
1
0
WRN
RDN
TXD1
RXD1
INT1
INT0
TXD0
RXD0
BIT
SYMBOL
ADDRESS
DESCRIPTION
7
6
5
4
3
2
1
0
WRN
RDN
TXD1
RXD1
INT1
INT0
TXD0
RXD0
0XB7H
0XB6H
0XB5H
0XB4H
0XB3H
0XB2H
0XB1H
0XB0H
WRN
WDN
TXD1: serial buffer 1; transmit
RXD1: serial buffer 1; receive
INT1: external Interrupt 1
INT0: external Interrupt 0
TXD0: serial buffer 0; transmit
RXD0: serial buffer 0; receive
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