參數(shù)資料
型號: SAA7324
廠商: NXP Semiconductors N.V.
英文描述: Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)(具有綜合數(shù)模轉(zhuǎn)換器(DAC)的數(shù)字伺服處理器和光盤譯碼器)
中文描述: 數(shù)字伺服處理器和光盤解碼器集成了援會(CD10型二)(具有綜合數(shù)模轉(zhuǎn)換器(DAC)的的數(shù)字伺服處理器和光盤譯碼器)
文件頁數(shù): 56/68頁
文件大?。?/td> 285K
代理商: SAA7324
2000 Jun 26
56
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)
SAA7324
11 OPERATING CHARACTERISTICS (I
2
S-BUS TIMING)
V
DD
= 3.0 to 3.6 V; V
SS
= 0 V; T
amb
=
10 to +70
°
C; unless otherwise specified.
Note
1.
The I
2
S-bus timing is directly related to the overspeed factor ‘n’ in the normal operating mode. In the lock-to-disc
mode ‘n’ is replaced by the disc speed factor ‘d’.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
2
S-bus timing (single-speed
×
n); see
Fig.33
; note
1
C
LOCK OUTPUT
:
PIN
SCLK (C
L
= 20
P
F)
T
cy
output clock period
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
166/n
83/n
42/n
166/n
83/n
42/n
472.4/n
236.2/n
118.1/n
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CH
clock HIGH time
t
CL
clock LOW time
O
UTPUTS
:
PINS
WCLK, DATA
AND
EF (C
L
= 20
P
F)
t
su
set-up time
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
95/n
48/n
24/n
95/n
48/n
24/n
ns
ns
ns
ns
ns
ns
t
h
hold time
VDD
0.8 V
VDD
0.8 V
tCH
MBG407
tCL
clock period Tcy
SCLK
WCLK
DATA
EF
th
tsu
Fig.33 I
2
S-bus timing diagram.
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