參數(shù)資料
型號: SAA7324
廠商: NXP Semiconductors N.V.
英文描述: Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)(具有綜合數(shù)模轉(zhuǎn)換器(DAC)的數(shù)字伺服處理器和光盤譯碼器)
中文描述: 數(shù)字伺服處理器和光盤解碼器集成了援會(CD10型二)(具有綜合數(shù)模轉(zhuǎn)換器(DAC)的的數(shù)字伺服處理器和光盤譯碼器)
文件頁數(shù): 22/68頁
文件大?。?/td> 285K
代理商: SAA7324
2000 Jun 26
22
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)
SAA7324
7.13
Spindle motor control
7.13.1
M
OTOR OUTPUT MODES
The spindle motor speed is controlled by a fully integrated
digital servo. Address information from the internal
±
8
frame FIFO and disc speed information are used to
calculate the motor control output signals. Several output
modes, selected by decoder register 6, are supported:
Pulse density, 2-line (true complement output),
(1
×
n) MHz sample frequency
PWM output, 2-line, (22.05
×
n) kHz modulation
frequency
PWM output, 4-line, (22.05
×
n) kHz modulation
frequency
CDV motor mode.
7.13.1.1
Pulse density output mode
In the pulse density mode the motor output pin (MOTO1)
is the pulse density modulated motor output signal. A 50%
duty factor corresponds with the motor not actuated,
higher duty factors mean acceleration, lower mean
braking. In this mode, the MOTO2 signal is the inverse of
the MOTO1 signal. Both signals change state only on the
edges of a (1
×
n) MHz internal clock signal. Possible
application diagrams are illustrated in Fig.14.
7.13.1.2
PWM output mode (2-line)
In the PWM mode the motor acceleration signal is put in
pulse-width modulation form on the MOTO1 output.
The motor braking signal is pulse-width modulated on the
MOTO2 output. The timing is illustrated in Fig.15. A typical
application diagram is illustrated in Fig.16.
MGA363 - 1
MOTO2
VDD
VSS
MOTO1
M
22 k
10 nF
+
22 k
10 nF
+
VSS
VSS
MOTO1
M
22 k
10 nF
+
22 k
22 k
VSS
VDD
VSS
22 k
22 k
Fig.14 Motor pulse density application diagrams.
trep
μ
s
tdead
Accelerate
Brake
MOTO1
MOTO2
MGA366
Fig.15 2-line PWM mode timing.
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