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參數(shù)資料
| 型號： | SAA7187 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital video encoder (DENC2-SQ)(數(shù)字視頻編碼器) |
| 中文描述： | 數(shù)字視頻編碼器（DENC2 -倚）（數(shù)字視頻編碼器） |
| 文件頁數(shù)： | 7/18頁 |
| 文件大小： | 197K |
| 代理商： | SAA7187 |
Philips Semiconductors
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
May 1994
7
4.0
RASTER CONTROL INPUT
SIGNALS,
SYNC-SLAVE-MODE
The internal synchronization circuitry of the
digital encoder SAA7187 and SAA7188A are
always defined by FISE (number of clocks
per line, subaddress 61hex), FLEN (number
of lines per field, subaddress 7Ahex and
7Dhex), and PAL (defining color field
sequence length, subaddress 61hex). In sync
slave mode, those horizontal and vertical
counters can be re-triggered by an external
trigger event at pin 6 as RCV1 input and/or at
pin 7 as RCV2 input. The rising or falling
edge can be selected as timing reference
(trigger event) to re-synchronize the internal
synchronization circuitry, regarding horizontal
or vertical counter, or odd-even flip-flop, or
color field sequence counter. As long as no
trigger event occurs the internal counters are
free running in the defined loops. Any single
occurance of the selected edge in RCV1 or
RCV2 input will hard re-trigger — i.e., it is not
a smoothed PLL procedure. Due to
processing pipeline delay, the resulting
re-synchronization does not take effect
before the next following corresponding
period. A programmable vertical and
horizontal trigger offset can be applied via
VTRIG and HTRIG.
RCV2 as input can also optionally be used as
“composite blanking” signal to gate the input
data stream, but only for data coming through
V-port (and D-port).
VTRIG represents a negative delay between
external trigger event and internal vertical
counter start, i.e., start of main vertical sync
(serration) pulses. The external
re-synchronization event at RCV1
over–writes the vertical counter state with
VTRIG value, which then synchronizes the
next vertical period to the external trigger
signal. VTRIG is defined with 5 bits under
subaddress 70 hex. The programmed VTRIG
number corresponds with the position of the
external trigger event along the field, counted
in half lines. Programming 00 will synchronize
the internal vertical counter to generate
vertical sync at the begin of that same half
line, in which the external trigger event
occurs. Programming of 1F hex results in
vertical sync output 31 half lines ahead of the
external trigger input, for example.
HTRIG represents a negative delay between
external trigger event and internal horizontal
counter start, i.e., leading edge of horizontal
sync pulse. The external re-synchronization
event at RCV1 or RCV2 over-writes the
horizontal counter state with HTRIG value,
which then synchronizes the next horizontal
period to the external trigger signal. HTRIG is
defined with 11 bits under subaddresses 6E
hex and 6F hex in LLC clock resolution, and
covers the whole line period. The
programmed HTRIG number corresponds
with its position (in LLC clocks) along the
scan line.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7188A | Digital Video Encoder (DENC2-M)(數(shù)字視頻編碼器(DENC2-M)) |
| SAA7201 | Integrated MPEG2 AVG Decoder(綜合MPEG音頻視頻圖表譯碼器) |
| SAA7201H | Integrated MPEG2 AVG decoder |
| SAA7212 | Integrated MPEG2 AVG Decoder(綜合MPEG音頻視頻圖表譯碼器) |
| SAA7212H | Integrated MPEG AVG decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7187WP | 制造商:NXP Semiconductors 功能描述: |
| SAA7188 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder DENC2-M |
| SAA7188A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder DENC2-M |
| SAA7188AWP | 制造商:NXP Semiconductors 功能描述:COLOR SIGNAL ENCODER, PQCC68 |
| SAA7191B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Multistandard Colour Decoder, Square Pixel DMSD-SQP |
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