參數(shù)資料
型號: SAA7187
廠商: NXP Semiconductors N.V.
英文描述: Digital video encoder (DENC2-SQ)(數(shù)字視頻編碼器)
中文描述: 數(shù)字視頻編碼器(DENC2 -倚)(數(shù)字視頻編碼器)
文件頁數(shù): 10/18頁
文件大?。?/td> 197K
代理商: SAA7187
Philips Semiconductors
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
May 1994
10
5.0
SYNC TIMING
DEPENDENCIES
The selected “active” edge of the external
timing reference signal RCV1 or RCV2 loads
the internal horizontal counter with the
HTRIG value. At the end of the line the
counter is automatically reset, and all timing
signals are in phase with the requesting
re-trigger. This horizontal counter also
defines the begin and end points of the raster
control output signals.
The effect of VTRIG for vertical
synchronization timing is very similar.
Figure 3. Horizontal ti ming for re-trigger and raster control output signal definition
RECV2 INPUT
HREF LIKE
RISING EDGE SELECTED
AS TIMING REFERENCE
INTERNAL
COUNTER
RESET
HTRIG
EMRQ
BMRQ
ERCV
BRCV
LOAD HTRIG
INTO COUNTER
OR
RCV INPUT
e.g., AS FS
INTERNAL
H-COUNTER
(SYMBOLIC)
RCM2 OUTPUT
OR
RCV2 OUTPUT
(HERE WITH NEGATIVE POLARITY)
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