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參數(shù)資料
| 型號： | SAA7120H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Digital video encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 27/36頁 |
| 文件大小： | 165K |
| 代理商： | SAA7120H |
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2002 Oct 11
27
Philips Semiconductors
Product specification
Digital video encoder
SAA7120H; SAA7121H
8.1
Explanation of RTCI data bits
1.
The HPLL increment is not evaluated by the
SAA7120H; SAA7121H.
The SAA7120H; SAA7121H generates the subcarrier
frequency from the FSCPLL increment if enabled
(see item 7.).
The PAL bit indicates the line with inverted (R
Y)
component of colour difference signal.
If the reset bit is enabled (RTCE = 1; DECPH = 1;
PHRES = 00), the phase of the subcarrier is reset in
each line whenever the reset bit of RTCI input is set to
logic 1.
If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the
SAA7120H; SAA7121H takes this bit instead of the
FISE bit in subaddress 61H.
2.
3.
4.
5.
6.
Iftheodd/evenbitisenabled(RTCE = 1;DECOE = 1),
the SAA7120H; SAA7121H ignores its internally
generated odd/even flag and takes the odd/even bit
from RTCI input.
If the colour detection bit is enabled (RTCE = 1;
DECCOL = 1) and no colour was detected (colour
detection bit = 0), the subcarrier frequency is
generated by the SAA7120H; SAA7121H. In the other
case (colour detection bit = 1) the subcarrier
frequency is evaluated out of FSCPLL increment.
If the colour detection bit is disabled (RTCE = 1;
DECCOL = 0), the subcarrier frequency is evaluated
out of FSCPLL increment, independent of the colour
detection bit of RTCI input.
7.
handbook, full pagewidth
128
13
14
19
67
64
69
72 74
68
0 1
0
0
22
RTCI
HPLL
increment
(1)
FSCPLL increment
(2)
count start
4 bits
reserved
valid
sample
invalid
sample
not used in SAA7120H/21H
3 bits
reserved
8/LLC
MBH789
LOW
time slot:
(3)
(4)
(6)
(7)
(8)
(5)
Fig.9 RTCI timing.
(1) SAA7111/12 provides 14 to 0 bits, resulting in 2 reserved bits before FSCPLL increment.
(2) SAA7151 provides 21 to 0 bits only, resulting in 5 reserved bits before sequence bit.
(3) Sequence bit: PAL: 0 = (R
Y) line normal, 1 = (R
Y) line inverted; NTSC: 0 = no change.
(4) Reset bit: only from SAA7111 and SAA7112 decoder.
(5) FISE bit: 0 = 50 Hz, 1 = 60 Hz.
(6) Odd/even bit: odd_even from external.
(7) Colour detection: 0 = no colour detected, 1 = colour detected.
(8) Reserved bits: 229 with 50 Hz systems, 226 with 60 Hz systems.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7120H-01 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder (ConDENC) |
| SAA7121 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder (ConDENC) |
| SAA7121H | 制造商:NXP Semiconductors 功能描述: |
| SAA7121H/V2 | 制造商:NXP Semiconductors 功能描述: |
| SAA7121H/V2,518 | 功能描述:視頻 IC SAA7121H/QFP44/REEL13DP//V2 RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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