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參數(shù)資料
| 型號： | SAA55XX |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) |
| 中文描述： | 與隱藏字幕（CC）和屏幕顯示（OSD電視微控制器） |
| 文件頁數(shù)： | 35/84頁 |
| 文件大?。?/td> | 352K |
| 代理商： | SAA55XX |
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2000 Feb 23
35
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
14.2
Tuning Pulse Width Modulator (TPWM)
The device has a single 14-bit PWM that can be used for
Voltage Synthesis Tuning. The method of operation is
similarto thenormal PWMexceptthat therepetition period
is 42.66
μ
s.
14.3
TPWM control
Two SFRs are used to control the TPWM, they are TDACL
and TDACH. The TPWM is enabled by setting the
TPWE bit in the TDACH SFR. The most significant bits
TD<13:7> alter the high period between 0 and 42.33
μ
s.
The seven least significant bits TD<6:0> extend certain
pulses by a further 0.33
μ
s, e.g. if TD<6:0> = 01H then
1 in 128 periods will be extended by 0.33
μ
s, if
TD<6:0> = 02H then 2 in 128 periods will be extended.
TheTPWMwillnotstarttooutputanewvalueuntilTDACH
has been written to. Therefore, if the value is to be
changed, TDACL should be written before TDACH.
14.4
Software ADC (SAD)
Four successive approximation Analog-to-Digital
Converterscanbeimplementedinsoftwarebymakinguse
of the on-board 8-bit Digital-to-Analog Converter and
Analog Comparator.
14.4.1
SAD
CONTROL
The control of the required analog input is done using the
channel select bits CH<1:0> in the SAD SFR, this selects
the required analog input to be passed to one of the inputs
of the comparator. The second comparator input is
generated by the DAC whose value is set by the bits
SAD<7:0> in the SAD and SADB SFRs. A comparison
between the two inputs is made when the start compare bit
ST in the SAD SFR is set, this must be at least one
instruction cycle after the SAD<7:0> value has been set.
The result of the comparison is given on VHI one
instruction cycle after the setting of ST.
14.4.2
SAD
INPUT VOLTAGE
The external analog voltage that is used for comparison
with the internally generated DAC voltage does not have
the same voltage range. The DAC has a lower reference
level of V
SSA
and an upper reference level of V
DDP
.
The resolution of the DAC voltage with a nominal value is
3.3
256
≈
13 mV. The external analog voltage has a lower
value equivalent to V
SSA
and an upper value equivalent to
V
DDP
V
tn
, where V
tn
is the threshold voltage for an N type
Metal Oxide Semiconductor transistor. The reason for this
is that the input pins for the analog signals (P3.0 to P3.3)
are 5 V tolerant for normal port operations, i.e. when not
used as analog input. To protect the analog multiplexer
and comparator circuitry from the 5 V, a series transistor is
used to limit the voltage. This limiting introduces a voltage
drop equivalent to V
tn
(
≈
0.6 V) on the input voltage. The
maximum value of V
tn
is 0.75 V, therefore for worst case
calculations, the maximum input to the SAD should be
calculated as V
DD(min)
0.75 V. Therefore, for an input
voltage in the range V
DDP
to V
DDP
V
tn
the SAD returns
the same comparison value.
14.4.3
SAD DC
COMPARATOR MODE
The SAD module incorporates a DC Comparator mode
which is selected using the DC_COMP control bit in the
SADB SFR. This mode enables the microcontroller to
detect a threshold crossing at the input to the selected
analog input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or
P3.3/ADC3) of the software ADC. A level sensitive
interrupt is generated when the analog input voltage level
at the pin falls below the analog output level of the SAD
DAC.
This mode is intended to provide the device with a
wake-up mechanism from Power-down or Idle mode when
a key-press on the front panel of the TV is detected.
The following software sequence should be used when
utilizing this mode for Power-down or Idle:
1.
Disable INT1 using the IE SFR.
2.
Set INT1 to level sensitive using the TCON SFR.
3.
Set the DAC digital input level to the desired threshold
level using SAD/SADB SFRs and select the required
input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or
P3.3/ADC3) using CH<1:0> in the SAD SFR.
4.
Enter DC Compare mode by setting the DC_COMP
enable bit in the SADB SFR.
5.
Enable INT1 using the IE SFR.
6.
Enter Power-down/Idle mode. Upon wake-up the SAD
should be restored to its conventional operating mode
by disabling the DC_COMP control bit.
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