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參數資料
| 型號： | SAA55XX |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) |
| 中文描述： | 與隱藏字幕（CC）和屏幕顯示（OSD電視微控制器） |
| 文件頁數： | 18/84頁 |
| 文件大?。?/td> | 352K |
| 代理商： | SAA55XX |
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2000 Feb 23
18
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
Port 1 (P1)
P17 to P10
Port 1 I/O register connected to external pins
Port 2 (P2)
P27 to P20
Port 2 I/O register connected to external pins
Port 3 (P3)
P37 to P30
Port 3 I/O register connected to external pins; P37 to P35 are only available with
the LQFP100 package
Port 0 Configuration A (P0CFGA) and Port 0 Configuration B (P0CFGB)
P0CFGA<7:0> and P0CFGB<7:0>
These two registers are used to configure Port 0 pins. For example, the I/O
configuration of Port 0 pin 3 is controlled using bit 3 in both P0CFGA and
P0CFGB. P0CFGB<x>/P0CFGA<x>:
00 = P0.x in open-drain configuration
01 = P0.x in quasi-bidirectional configuration
10 = P0.x in high-impedance configuration
11 = P0.x in push-pull configuration
Port 1 Configuration A (P1CFGA) and Port 1 Configuration B (P1CFGB)
P1CFGA<7:0> and P1CFGB<7:0>
These two registers are used to configure Port 1 pins. For example, the I/O
configuration of Port 1 pin 3 is controlled using bit 3 in both P1CFGA and
P1CFGB. P1CFGB<x>/P1CFGA<x>:
00 = P1.x in open-drain configuration
01 = P1.x in quasi-bidirectional configuration
10 = P1.x in high-impedance configuration
11 = P1.x in push-pull configuration
Port 2 Configuration A (P2CFGA) and Port 2 Configuration B (P2CFGB)
P2CFGA<7:0> and P2CFGB<7:0>
These two registers are used to configure Port 2 pins. For example, the I/O
configuration of Port 2 pin 3 is controlled by using bit 3 in both P2CFGA and
P2CFGB. P2CFGB<x>/P2CFGA<x>:
00 = P2.x in open-drain configuration
01 = P2.x in quasi-bidirectional configuration
10 = P2.x high-impedance configuration
11 = P2.x push-pull configuration
Port 3 Configuration A (P3CFGA) and Port 3 Configuration B (P3CFGB)
P3CFGA<7:0> and P3CFGB<7:0>
These two registers are used to configure Port 3 pins. For example, the I/O
configuration of Port 3 pin 3 is controlled using bit 3 in both P3CFGA and
P3CFGB. P3CFGB<x>/P3CFGA<x>:
00 = P3.x in open-drain configuration
01 = P3.x in quasi-bidirectional configuration
10 = P3.x in high-impedance configuration
11 = P3.x in push-pull configuration
BIT
FUNCTION
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