參數(shù)資料
型號: SA25F020LEN
廠商: Electronic Theatre Controls, Inc.
英文描述: RES 82.5 OHM 1/10W .5% 0805 SMD
中文描述: 2MB的串行閃存與25MHz的SPI總線接口
文件頁數(shù): 28/37頁
文件大?。?/td> 560K
代理商: SA25F020LEN
SA25F020 Advanced Information
SAIFUN
28
Sector Erase (SE)
The SE instruction sets all 512 Kb in the
selected sector to 1. Before it can be
executed, two separate instructions must
be carried out. The device must first be
write enabled via the WREN instruction,
and then a SE sequence, which consists of
four bytes, may be executed. The address
of the memory locations to be written must
be inside the sector to be erased and
outside the protected address field location
selected by the Block Write Protection
level. During an internal SE cycle, all
commands are ignored except the RDSR
instruction.
A SE instruction requires the following
sequence:
1. After the CSb line is pulled low to
select the device, the SE opcode is
transmitted via the SI line, followed
by the 3-byte address.
2. Erasing begins after the CSb pin is
brought high. The CSb pin's
low-to-high transition must occur
during
the
immediately after the clock in the
last address bit.
SCK
low
time,
As soon as CSb is driven high, the
self-timed SE cycle (whose duration is
defined as T
SE
) is initiated. While the SE
cycle is in progress, the status register
may be read to check the value of the
/RDY bit. The /RDY bit is 1 during the
self-timed SE cycle, and 0 when it is
completed. The WEN bit is reset at some
unspecified time before the cycle is
completed. The instruction sequence is
shown in Figure 18.
The SA25F020 is automatically returned to
the write disable state at the completion of
an SE cycle.
NOTES:
1. If the device is not write enabled,
the
device
ignores
instruction and returns to the
standby state when CSb is brought
high. A new CSb falling edge is
required to re-initiate the serial
communication.
2. A SE instruction applied to a sector
that is protected by the Block
Protect
(BP1,
described in Table 8, page 18, and
Table 9, page 21) is not executed.
the
SE
BP0)
bits
(as
1
3
2
10
9
8
7
6
5
4
0
31
30
29
28
Instruction
24 Bit Address
23
21
22
1
3
2
0
SCK
SI
MSB
CS
Figure 18. Sector Erase (SE) Instruction Sequence
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