參數(shù)資料
型號: SA25F020LEN
廠商: Electronic Theatre Controls, Inc.
英文描述: RES 82.5 OHM 1/10W .5% 0805 SMD
中文描述: 2MB的串行閃存與25MHz的SPI總線接口
文件頁數(shù): 18/37頁
文件大?。?/td> 560K
代理商: SA25F020LEN
SA25F020 Advanced Information
SAIFUN
18
In addition to the instruction register, the
device also contains an 8-bit status register
that can be accessed by RDSR and WRSR
instructions. The byte defines the Block
Write Protection (BP1 and BP0) levels,
Write Enable (WEN) status, Busy/Rdy
(/RDY) status and Hardware Write Protect
(WPBEN) status of the device. Table 7
illustrates the format of the status register.
Table 7. Status Register Format
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit1 Bit 0
WPBEN X
X
X
BP1 BP0 WEN /RDY
Read Status Register (RDSR)
The RDSR instruction provides read
access to the status register. The
BUSY/RDY and WREN statuses of the
device can also be determined by this
instruction. In addition, the Block Write
Protection bits indicate the extent of
protection employed. In order to determine
the status of the device, the value of the
/RDY bit can be continuously polled before
sending any write instruction.
Table 8. Read Status Register Definition
Bit
Definition
Bit 0 (/RDY)
Bit 0 = 0 (/RDY) indicates that the
device is READY.
Bit 0 = 1 indicates that a write
cycle is in progress.
Bit 1 (WEN)
Bit 1 = 0 indicates that the device
is not write enabled.
Bit 1 = 1 indicates that the device
is write enabled.
Bit 2 (BP0)
Block Write Protect Bit 0
Bit 3 (BP1)
Block Write Protect Bit 1
Bit 7
(WPBEN)
Write Protect Mode Enable Bit
Bit 7 (WPBEN) is Hardware Write Protect
mode. If this bit is a 1, this mode is enabled
and the status register is write protected.
Bits 6 through 4 are always 0.
Bit 3 (BP1) and Bit 2 (BP0) together
indicate a Block Write Protection previously
sent to the device.
Bits 0 and 1 are 1 during an internal write
cycle.
Bit 1 (WEN) indicates the Write Enable
status of the device. This bit is read by
executing an RDSR instruction. If this bit is
1, the device is write enabled; if it is 0, it is
write disabled.
Bit 0 (/RDY) indicates the Busy/Ready
status of the device. This bit is a read-only
bit and is read by executing an RDSR
instruction. If this bit is 1, the device is busy
doing a Program or Erase cycle; if it is 0,
the device is ready.
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