參數(shù)資料
型號(hào)： S80296SA40
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100
封裝： QFP-100
文件頁(yè)數(shù)： 5/40頁(yè)
文件大?。?/td> 1096K
代理商： S80296SA40
PRELIMINARY
9
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
NMI
I
Nonmaskable Interrupt
In normal operating mode, a rising edge on NMI generates a nonmaskable interrupt.
NMI has the highest priority of all interrupts except trap and unimplemented opcode.
Assert NMI for greater than one state time to guarantee that it is recognized.
If NMI is held high during and immediately following reset, the microcontroller will
execute the NMI interrupt service routine when code execution begins. To prevent
an inadvertent NMI interrupt vector, the first instruction (at F2080H) must clear the
NMI pending interrupt bit.
ANDB INT_PEND1, #7FH.
During idle mode, a rising edge on NMI causes the microcontroller to exit idle mode
and branch to the interrupt service routine.
ONCE
I
On-circuit Emulation
Holding ONCE high during the rising edge of RESET# places the microcontroller
into on-circuit emulation (ONCE) mode. This mode puts all pins, except READY,
RESET#, ONCE, and NMI, into a high-impedance state, thereby isolating the
microcontroller from other components in the system. The value of ONCE is latched
when the RESET# pin goes inactive. While the microcontroller is in ONCE mode,
you can debug the system using a clip-on emulator.
To exit ONCE mode, reset the microcontroller by pulling the RESET# signal low. To
prevent inadvertent entry into ONCE mode, connect the ONCE pin to V
SS.
P1.7:0
I/O
Port 1
This is a standard, 8-bit, bidirectional port that shares package pins with individually
selectable special-function signals.
Port 1 shares package pins with the following signals: P1.0/EPA0, P1.1/EPA1,
P1.2/EPA2, P1.3/EPA3, P1.4/T1CLK, P1.5/T1DIR, P1.6/T2CLK, and P1.7/T2DIR.
P2.7:0
I/O
Port 2
This is a standard, 8-bit, bidirectional port that shares package pins with individually
selectable special-function signals.
Port 2 shares package pins with the following signals: P2.0/TXD, P2.1/RXD,
P2.2/EXTINT0, P2.3/BREQ#, P2.4/EXTINT1, P2.5/HOLD#, P2.6/HLDA#, and
P2.7/CLKOUT.
P3.7:0
I/O
Port 3
This is a standard, 8-bit, bidirectional port that shares package pins with individually
selectable special-function signals.
Port 3 shares package pins with the following signals: P3.0/CS0#, P3.1/CS1#,
P3.2/CS2#, P3.3/CS3#, P3.4/CS4#, P3.5/CS5#, P3.6/EXTINT2, and
P3.7/EXTINT3.
P4.3:0
I/O
Port 4
Port 4 is a standard, 4-bit, bidirectional I/O port with high-current drive capability.
Port 4 shares package pins with the following signals: P4.0/PWM0, P4.1/PWM1,
and P4.2/PWM2. P4.3 has a dedicated package pin.
Table 4. Signal Descriptions (Continued)
Name
Type
Description
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