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參數(shù)資料
| 型號： | S80296SA40 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 26/40頁 |
| 文件大?。?/td> | 1096K |
| 代理商： | S80296SA40 |
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PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.4.3
80296SA Deferred Bus Timing Mode
The deferred bus cycle mode is designed to reduce bus contention when using the 80296SA in demultiplexed
mode with slow memory devices. Unlike the 8XC196NU, in which this bus mode has to be enabled through
the CCR to take advantage of the feature, the 80296SA automatically invokes this mode whenever the
appropriate conditions occur. In the deferred mode, a delay of the WR# signal and the next bus cycle will
occur in the first bus cycle following a chip-select change and in the first write cycle following a read cycle.
This mode will work in parallel with wait states. Refer to Figure 11 to determine which control signals are
affected.
Cycle 1 is a normal 4t read cycle. Cycle 2 is a write cycle that follows a read cycle, so a 2t delay of the next
bus cycle is inserted. Notice that the chip-select change at the beginning of cycle 2 did not cause a double
delay (4t). The chip-select change in cycle 3, a read cycle, causes a 2t delay.
Figure 10. Deferred Bus Mode Timing Diagram
CLKOUT
ALE
RD#
A3247-02
TWHLH + 2t
TRHLH + 2t
TAVRL + 2t
TAVWL + 2t
AD15:0
(read)
WR#
AD15:0
(write)
BHE#, INST
A19:0
CS
x#
TAVDV + 2t
TLHLH + 2t
Data In
Data Out
Valid
Data Out
Address Out
Data Out
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