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參數(shù)資料
| 型號： | S80296SA40 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 21/40頁 |
| 文件大?。?/td> | 1096K |
| 代理商： | S80296SA40 |
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24
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.4
AC CHARACTERISTICS — DEMULTIPLEXED BUS MODE
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 10. AC Characteristics the 80C296SA Will Meet, Demultiplexed Bus Mode
Symbol
Parameter
Min
Max
Units
F
XTAL
1
Frequency on XTAL1, PLL in 1x mode
16
50 (1)
MHz
Frequency on XTAL1, PLL in 2x mode
8 (2)
25
MHz
Frequency on XTAL1, PLL in 4x mode
8 (2)
12.5
MHz
f
Operating frequency, f = F
XTAL
1; PLL in 1x mode
16
50
MHz
Operating frequency, f = 2F
XTAL
1; PLL in 2x mode
Operating frequency, f = 4F
XTAL
1; PLL in 4x mode
t
Period, t = 1/f
20
62.5
ns
T
AVWL
Address Valid to WR# Falling Edge
t – 10
ns
T
AVRL
Address Valid to RD# Falling Edge
t – 10
ns
T
RHRL
Read High to Next Read Low
t – 5
ns
T
XHCH
XTAL1 High to CLKOUT High or Low
3
50
ns
T
CLCL
CLKOUT Cycle Time
2t
ns
T
CHCL
CLKOUT High Period
t – 10
t + 15
ns
T
CLLH
CLKOUT Falling Edge to ALE Rising Edge
–13
10
ns
T
LLCH
ALE Falling Edge to CLKOUT Rising Edge
–15
15
ns
T
LHLH
ALE Cycle Time
4t
ns (3,4)
T
LHLL
ALE High Period
t – 10
t + 10
ns
T
RLCL
RD# Low to CLKOUT Falling Edge
–5
11
ns
T
RLRH
RD# Low Period
3t – 18
ns (3)
T
RHLH
RD# Rising Edge to ALE Rising Edge
t – 4
t + 15
ns (4)
T
WLCL
WR# Low to CLKOUT Falling Edge
–8
9
ns
T
QVWH
Data Stable to WR# Rising Edge
3t – 10
ns (4)
T
CHWH
CLKOUT High to WR# Rising Edge
–11
10
ns
T
WLWH
WR# Low Period
3t – 10
ns (3)
T
WHQX
Data Hold after WR# Rising Edge
t – 5
t + 20
ns
T
WHLH
WR# Rising Edge to ALE Rising Edge
t – 5
t + 10
ns (3)
NOTES:
1.
25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz
can be applied with an external clock source.
2.
When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8
MHz. The PLL cannot be run at frequencies lower than 16 MHz.
3.
If using either READY or BUSCON
x to insert wait states, add 2t
× n, where n = number of wait states.
4.
Assuming back-to-back bus cycles.
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