參數(shù)資料
型號: S80296SA40
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100
封裝: QFP-100
文件頁數(shù): 32/40頁
文件大?。?/td> 1096K
代理商: S80296SA40
34
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
tics” is Section 6.0; “Errata” is Section 8.0, and “Datasheet Revision History” is Section 9.0.
6.
Table 2 was changed to Table 1 and the “process information” was corrected to show that “no mark” sig-
nifies a CHMOS process.
7.
Table 3 was changed to Table 7 and several clarifications were made.
8.
Figure 3 was changed to correct the product name. Pin assignments did not change.
9.
Table 4 was changed to Table 2 and pin 3 was changed from “no connection” to “tie to V
CC.”
10. Figure 4 was changed to correct the product name. Pin assignments did not change.
11. Figure 5, “I
CC versus Frequency in Reset,” was added. Remaining figure numbers were incremented.
12. Table 6 was changed to Table 4 and a note for handling the “no connection” pins was added.
13. Table 8 was changed to Table 6. The descriptions of BREQ#, HLDA#, and HOLD# were changed to
reflect their operation during hold. The description of the ONCE signal was changed to reflect the correct
states of READY, RESET#, and NMI during ONCE mode. The description of PLLEN2:1 was changed to
show the correct pin states to achieve each phase-locked loop (PLL) clock multiplier mode. The descrip-
tions of RPD and RESET# were changed to reflect system requirements when using the PLL.
14. Two notes were added to clarify the “Operating Conditions” in the “Electrical Characteristics” section.
15. Table 9 was changed to Table 8, the notes were re-ordered, and the following specifications were
changed:
I
CC max was changed to 150 mA
(from 120 mA).
V
OH min was changed to VCC–0.5 V
(from V
CC–0.3 V) at IOH = –200A.
V
OH min was changed to VCC–0.9 V
(from V
CC–0.7V) at IOH = –3.2 mA.
Test condition for V
OL
1 max = 0.45 V was changed to IOL = 8 mA (from IOL = 10 mA).
R
RST min and max were changed to 50 k and 150 k (from 9 k and 95 k).
V
OH
3 min specification was added.
16. Table 10 was divided into two tables: timing specifications that the microcontroller will meet (Table 10)
and those that the external memory system must meet (Table 11). Note 7 was deleted and the remain-
ing notes were re-ordered. The following specifications were changed or added in Table 10:
F
XTAL
1 min for the PLL in 4x mode was changed to 8 MHz (from 4 MHz); a clarifying note was added.
T
XHCH min was changed to 3 ns (from TBD).
T
LLAX min was changed to 1 ns (from TBD).
T
LLRL min was changed to 3 ns (from TBD)
T
RHAX min was changed to t – 4 ns (from t).
T
AVWL min (2t – 25) was added to Table 10.
T
SLDV min (4t – 28) was added to Table 11.
17. Table 11 was divided into two tables: timing specifications that the microcontroller will meet (Table 12)
and those that the external memory system must meet (Table 13). Note 7 was deleted and the remain-
ing notes were re-ordered. The following specifications were changed:
F
XTAL
1 min for the PLL in 4x mode was changed to 8 MHz (from 4 MHz); a clarifying note was added.
T
WHQX min was changed to t – 5 ns (from t – 2 ns).
18. Figure 6 was changed to show the correct PLLEN2:1 values to select the 2x clock multiplier mode.
19. Table 13 was changed to Table 15 and a note was added.
20. Table 14 was changed to Table 16, 1/T
XLXL specifications for each phase-locked loop (PLL) mode were
added, and Note 2 was deleted.
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