參數(shù)資料
型號: S71PL129JC0BFW9Z2
廠商: SPANSION LLC
元件分類: 存儲(chǔ)器
英文描述: Stacked Multi-Chip Product (MCP) Flash Memory
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA64
封裝: 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-64
文件頁數(shù): 21/153頁
文件大?。?/td> 3651K
代理商: S71PL129JC0BFW9Z2
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
115
Advance
Informatio n
Mode Register Update and Deep Sleep Timings
Notes:
1. Minimum cycle time for writing register is equal to speed grade of product.
Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M)
Figure 42. Deep Sleep Mode - Entry/Exit Timings (for 32M and 16M)
Item
Symbol
Min
Max
Unit
Note
Chip deselect to ZZ# low
tCDZZ
5
ns
ZZ# low to WE# low
tZZWE
10
500
ns
Write register cycle time
tWC
70/85
ns
1
Chip enable to end of write
tCW
70/85
ns
1
Address valid to end of write
tAW
70/85
ns
1
Write recovery time
tWR
0
ns
Address setup time
tAS
0
ns
Write pulse width
tWR
40
ns
Deep Sleep Pulse Width
tZZMIN
10
s
Deep Sleep Recovery
tR
200
s
ZZ#
tZZMIN
tCDZZ
tR
CE#
A4
ZZ#
tWC
tBW
tAS
CE#
WE#
tZZWE
tAW
tWP
tWR
tR
tZZMIN
LB#, UB#
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