參數(shù)資料
型號： S71PL129JC0BFW9Z2
廠商： SPANSION LLC
元件分類： 存儲器
英文描述： Stacked Multi-Chip Product (MCP) Flash Memory
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA64
封裝： 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-64
文件頁數(shù)： 109/153頁
文件大小： 3651K
代理商： S71PL129JC0BFW9Z2
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
57
Advance
Informatio n
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide
an address within any of the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 400 s, then the
bank returns to the read mode. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
When the system detects DQ7 has changed from the complement to true data,
it can read valid data at DQ15–DQ0 on the following read cycles. Just prior to the
completion of an Embedded Program or Erase operation, DQ7 may change asyn-
chronously with DQ15–DQ0 while Output Enable (OE#) is asserted low. That is,
the device may change from providing status information to valid data on DQ7.
Depending on when the system samples the DQ7 output, it may read the status
or valid data. Even if the device has completed the program or erase operation
and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid
data on DQ15–DQ0 appears on successive read cycles.
Table 14 shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling
algorithm. Figure 18 in AC Characteristics shows the Data# Polling timing
diagram.
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